FAN5026 Просмотр технического описания (PDF) - Fairchild Semiconductor

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FAN5026

Dual DDR/Dual-Output PWM Controller

Fairchild Semiconductor 

Setting the Current Limit

A ratio of ISNS is also compared to the current

established when a 0.9 V internal reference drives the

ILIM pin. The threshold is determined at the point when

the I---S---9-N-----S-- > I---L---I--M--3-----×-----4- . Since

ISNS = -I-L--1-O--0--A--0--D--+---×--R--R---S--D-E---S-N--(--SO---E-N----) therefore,

ILIMIT = -R-0---.I--9L---IV-M--- × 43-- × 9-----×-----(---1--R-0---0-D----S+---(--RO----N-S---)E----N---S----E----)

(3a)

or

RILIM = -I-1L---I-0-M--.--8I--T- × -(--1---0----0-R---+-D----SR---(--SO---E-N---N-)---S---E----)

(3b)

Since the tolerance on the current limit is largely depen-

dent on the ratio of the external resistors, it is fairly accu-

rate if the voltage drop on the Switching Node side of

RSENSE is an accurate representation of the load current.

When using the MOSFET as the sensing element, the

variation of RDS(ON) causes proportional variation in the

ISNS. This value not only varies from device to device,

but also has a typical junction temperature coefficient of

about 0.4%/°C (consult the MOSFET datasheet for

actual values), so the actual current limit set point will

decrease proportional to increasing MOSFET die tem-

perature. A factor of 1.6 in the current limit setpoint

should compensate for all MOSFET RDS(ON) variations,

assuming the MOSFET’s heat sinking will keep its oper-

ating die temperature below 125°C.

Q2

LDRV

ISNS RSENSE

PGND

Figure 11. Improving Current Sensing Accuracy

More accurate sensing can be achieved by using a resis-

tor (R1) instead of the RDS(ON) of the FET as shown in

Figure 11. This approach causes higher losses, but

yields greater accuracy in both VDROOP and ILIMIT. R1 is

a low value (e.g. 10mΩ) resistor.

Current limit (ILIMIT) should be set sufficiently high as to

allow inductor current to rise in response to an output

load transient. Typically, a factor of 1.3 is sufficient. In

addition, since ILIMIT is a peak current cut-off value, we

will need to multiply ILOAD(MAX) by the inductor ripple cur-

rent (we'll use 25%). For example, in Figure 5 the target

for ILIMIT would be:

ILIMIT > 1.2 × 1.25 × 1.6 × 6A ≈ 14A

(4)

Gate Driver Section

The adaptive gate control logic translates the internal

PWM control signal into the MOSFET gate drive signals

providing necessary amplification, level shifting and

shoot-through protection. Also, it has functions that help

optimize the IC performance over a wide range of oper-

ating conditions. Since MOSFET switching time can vary

dramatically from type to type and with the input voltage,

the gate control logic provides adaptive dead time by

monitoring the gate-to-source voltages of both upper and

lower MOSFETs. The lower MOSFET drive is not turned

on until the gate-to-source voltage of the upper MOSFET

has decreased to less than approximately 1 volt. Simi-

larly, the upper MOSFET is not turned on until the gate-

to-source voltage of the lower MOSFET has decreased

to less than approximately 1 volt. This allows a wide vari-

ety of upper and lower MOSFETs to be used without a

concern for simultaneous conduction, or shoot-through.

There must be a low-resistance, low-inductance path

between the driver pin and the MOSFET gate for the

adaptive dead-time circuit to work properly. Any delay

along that path will subtract from the delay generated by

the adaptive dead-time circuit and shoot-through may

occur.

Frequency Loop Compensation

Due to the implemented current mode control, the modu-

lator has a single pole response with -1 slope at fre-

quency determined by load

FPO = 2----π----R---1-O----C-----O--

(5)

where RO is load resistance and CO is load capacitance.

For this type of modulator, Type 2 compensation circuit is

usually sufficient. To reduce the number of external com-

ponents and simplify the design task, the PWM controller

has an internally compensated error amplifier. Figure 12

shows a Type 2 amplifier and its response along with the

responses of a current mode modulator and of the con-

verter. The Type 2 amplifier, in addition to the pole at the

origin, has a zero-pole pair that causes a flat gain region

at frequencies between the zero and the pole.

FZ = -2---π----R--1--2---C-----1- = 6kHz

(6a)

FP = -2---π----R--1--2---C-----2- = 600kHz

(6b)

This region is also associated with phase ‘bump’ or

reduced phase shift. The amount of phase shift reduction

depends the width of the region of flat gain and has a

maximum value of 90 degrees. To further simplify the

converter compensation, the modulator gain is kept inde-

pendent of the input voltage variation by providing feed-

forward of VIN to the oscillator ramp.

11

FAN5026 Rev. 1.0.5

www.fairchildsemi.com

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