FAN5026 Просмотр технического описания (PDF) - Fairchild Semiconductor

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FAN5026

Dual DDR/Dual-Output PWM Controller

Fairchild Semiconductor 

5V

RD

VIN

HDRV

SW

C GD

RGATE

G

CGS

Figure 16. Drive Equivalent Circuit

tS = I-Q-D----GR----(I--VS---EW---R--) ≈ ---R----------D--------R--V-----I---CV-Q-------E--C-G---R-----(---–S--+------WV----R----S-)---G----P----A--------T------E------

(18)

Most MOSFET vendors specify QGD and QGS. QG(SW)

can be determined as: QG(SW) = QGD + QGS – QTH where

QTH is the gate charge required to get the MOSFET to it’s

threshold (VTH). For the high-side MOSFET, VDS = VIN,

which can be as high as 20V in a typical portable

application. Care should also be taken to include the

delivery of the MOSFET’s gate power (PGATE) in

calculating the power dissipation required for the

FAN5026:

PGATE = QG × VCC × FSW

(19)

where QG is the total gate charge to reach VCC.

Low-Side Losses

Q2, however, switches on or off with its parallel shottky

diode conducting, therefore VDS ≈ 0.5V. Since PSW is pro-

portional to VDS, Q2’s switching losses are negligible and

we can select Q2 based on RDS(ON) only.

Conduction losses for Q2 are given by:

PCOND

=

(1

–

D)

×

IO

U

2

T

×

RDS(ON)

(20)

where RDS(ON) is the RDS(ON) of the MOSFET at the

highest operating junction temperature and

D = V---V--O---I-UN---T--

is the minimum duty cycle for the converter.

Since DMIN < 20% for portable computers, (1–D) ≈ 1

produces a conservative result, further simplifying the

calculation.

The maximum power dissipation (PD(MAX)) is a function of

the maximum allowable die temperature of the low-side

MOSFET, the θJ-A, and the maximum allowable ambient

temperature rise:

PD(MAX) = T----J---(--M----A----X-θ--)--J-–--–---T-A---A---(--M----A----X---)

(21)

θJ-A, depends primarily on the amount of PCB area

that can be devoted to heat sinking (see FSC app note

AN-1029 for SO-8 MOSFET thermal information).

Layout Considerations

Switching converters, even during normal operation,

produce short pulses of current which could cause

substantial ringing and be a source of EMI if layout

constrains are not observed.

There are two sets of critical components in a DC-DC

converter. The switching power components process large

amounts of energy at high rate and are noise generators.

The low power components responsible for bias and

feedback functions are sensitive to noise.

A multi-layer printed circuit board is recommended.

Dedicate one solid layer for a ground plane. Dedicate

another solid layer as a power plane and break this plane

into smaller islands of common voltage levels.

Notice all the nodes that are subjected to high dV/dt

voltage swing such as SW, HDRV and LDRV, for example.

All surrounding circuitry will tend to couple the signals

from these nodes through stray capacitance. Do not

oversize copper traces connected to these nodes. Do not

place traces connected to the feedback components

adjacent to these traces. It is not recommended to use

High Density Interconnect Systems, or micro-vias on

these signals. The use of High Density Interconnect

Systems or micro-vias on these signals is not

recommended. The use of normal thermal vias is left to

the discretion of the designer.

Keep the wiring traces from the IC to the MOSFET gate

and source as short as possible and capable of handling

peak currents of 2A. Minimize the area within the gate-

source path to reduce stray inductance and eliminate

parasitic ringing at the gate.

Locate small critical components like the soft-start

capacitor and current sense resistors as close as possible

to the respective pins of the IC.

The FAN5026 utilizes advanced packaging technologies

with lead pitches of 0.6mm. High performance analog

semiconductors utilizing narrow lead spacing may require

special considerations in PWB design and manufacturing.

It is critical to maintain proper cleanliness of the area

surrounding these devices. It is not recommended to use

any type of rosin or acid core solder, or the use of flux in

either the manufacturing or touch up process as these

may contribute to corrosion or enable electromigration

and/or eddy currents near the sensitive low current

signals. When chemicals such as these are used on or

near the PWB, it is suggested that the entire PWB be

cleaned and dried completely before applying power.

15

FAN5026 Rev. 1.0.5

www.fairchildsemi.com

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