FAN5026 Просмотр технического описания (PDF) - Fairchild Semiconductor

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FAN5026

Dual DDR/Dual-Output PWM Controller

Fairchild Semiconductor 

C2

R2 C1

R1

VIN

REF

EA Out

error amp

Converter

modulator

18

14

0

F

F

F

P0

Z

P

Figure 12. Compensation

The zero frequency, the amplifier high frequency gain

and the modulator gain are chosen to satisfy most typical

applications. The crossover frequency will appear at the

point where the modulator attenuation equals the ampli-

fier high frequency gain. The only task that the system

designer has to complete is to specify the output filter

capacitors to position the load main pole somewhere

within one decade lower than the amplifier zero fre-

quency. With this type of compensation plenty of phase

margin is easily achieved due to zero-pole pair phase

‘boost’.

Conditional stability may occur only when the main load

pole is positioned too much to the left side on the fre-

quency axis due to excessive output filter capacitance. In

this case, the ESR zero placed within the 10kHz...50kHz

range gives some additional phase ‘boost’. Fortunately,

there is an opposite trend in mobile applications to keep

the output capacitor as small as possible.

If a larger inductor value or low ESR values are called for

by the application, additional phase margin can be

achieved by putting a zero at the LC crossover fre-

quency. This can be achieved with a capacitor across the

feedback resistor (e.g. R5 from Figure 5) as shown

below.

L(OUT)

VOUT

R5 C(Z) C(OUT)

VSEN

R6

Figure 13. Improving Phase Margin

The optimal value of C(Z) is:

C(Z) = -----L---(---O-----U-----T---R-)---×-5----C-----(--O-----U-----T----)

(7)

Protection

The converter output is monitored and protected against

extreme overload, short circuit, over-voltage and under-

voltage conditions.

A sustained overload on an output sets the PGx pin low

and latches-off the whole chip. Operation can be

restored by cycling the VCC voltage or by toggling the

EN pin.

If VOUT drops below the under-voltage threshold, the

chip shuts down immediately.

Over-Current Sensing

If the circuit’s current limit signal (“ILIM det” as shown in

Figure 10) is high at the beginning of a clock cycle, a

pulse-skipping circuit is activated and HDRV is inhibited.

The circuit continues to pulse skip in this manner for the

next 8 clock cycles. If at any time from the 9th to the 16th

clock cycle, the “ILIM det” is again reached, the over-

current protection latch is set, disabling the chip. If “ILIM

det” does not occur between cycle 9 and 16, normal oper-

ation is restored and the over-current circuit resets itself.

1

IL

2

PGOOD

8 CLK

VOUT

SHUTDOWN

3

CH1 5.0V

CH3 2.0AΩ

CH2 100mV

M 10.0µs

Figure 14. Over-Current Protection Waveforms

Over-Voltage / Under-Voltage Protection

Should the VSNS voltage exceed 120% of VREF (0.9V)

due to an upper MOSFET failure, or for other reasons,

the overvoltage protection comparator will force LDRV

high. This action actively pulls down the output voltage

and, in the event of the upper MOSFET failure, will even-

tually blow the battery fuse. As soon as the output volt-

age drops below the threshold, the OVP comparator is

disengaged.

This OVP scheme provides a ‘soft’ crowbar function

which helps to tackle severe load transients and does

not invert the output voltage when activated — a com-

mon problem for latched OVP schemes.

12

FAN5026 Rev. 1.0.5

www.fairchildsemi.com

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