FAN5026 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FAN5026 Datasheet PDF : 17 Pages
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As an example, if average IVDDQ is 3A, and average IVTT
is 1A, IVDDQ current will be about 3.5A. If average input
voltage is 12V, RMS input ripple current will be:
IRMS = IOUT(MAX) D – D2
(13)
where D is the duty cycle of the PWM1 converter:
D < V---V--O---I-UN---T-- = 2-1---.-2-5-
(14)
therefore:
IRMS = 3.5
2-1---.-2-5-
–
2-1---.-2-5-
2
=
1.42A
(15)
Dual Converter 180° Phased
In Dual mode (Figure 5), both converters contribute to
the capacitor input ripple current. With each converter
operating 180° out of phase, the RMS currents add in the
following fashion:
IRMS =
IR
MS
2
(1)
+
IR
M
S
(
2
2)
or
(16a)
IRMS = (I1)2(D1 – D12) + (I2)2(D2 – D22)
(16b)
which for the dual 3A converters of Figure 5, calculates
to:
IRMS = 1.51A
Power MOSFET Selection
Losses in a MOSFET are the sum of its switching (PSW)
and conduction (PCOND) losses.
In typical applications, the FAN5026 converter’s output
voltage is low with respect to its input voltage, therefore
the Lower MOSFET (Q2) is conducting the full load cur-
rent for most of the cycle. Q2 should therefore be
selected to minimize conduction losses, thereby select-
ing a MOSFET with low RDS(ON).
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle, and it's conduction loss will therefore
have less of an impact. Q1, however, sees most of the
switching losses, so Q1’s primary selection criteria
should be gate charge.
High-Side Losses
Figure shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the Drain
to Source and the lower graph detailing VGS vs. time with
a constant current charging the gate. The x-axis there-
fore is also representative of gate charge (QG). CISS =
CGD + CGS, and it controls t1, t2, and t4 timing. CGD
receives the current from the gate driver during t3 (as
VDS is falling). The gate charge (QG) parameters on the
lower graph are either specified or can be derived from
MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses,
occur during the shaded time when the MOSFET has
voltage across it and current through it.
These losses are given by:
PUPPER = PSW + PCOND
PSW
=
V-----D---S-----×-----I--L-
2
×
2
×
tS
FSW
(17a)
PCOND
=
V---V--O---I-UN---T--
× IOUT2 × RDS(ON)
(17b)
where:
PUPPER is the upper MOSFET’s total losses, and PSW
and PCOND are the switching and conduction losses for a
given MOSFET. RDS(ON) is at the maximum junction tem-
perature (TJ). tS is the switching period (rise or fall time)
and is t2+t3 Figure .
The driver’s impedance and CISS determine t2 while t3’s
period is controlled by the driver's impedance and QGD.
Since most of tS occurs when VGS = VSP we can use a
constant current assumption for the driver to simplify the
calculation of tS:
VDS
CISS
C GD
C ISS
ID
VSP
VTH
VGS
QGS
QGD
QG(SW)
t1
t2
t3
4.5V
t4
t5
Figure 15. Switching Losses and QG
14
FAN5026 Rev. 1.0.5
www.fairchildsemi.com
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