DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

Loopbacks: remote, local, analog, and per-channel

loopback

Extended System Information Bus

Host can read interrupt and alarm status on up to 8

ports with a single bus read

User-Programmable Output Pins

Four user-defined output pins for controlling

external logic

DS2156

Control Port

8-bit parallel control port

Multiplexed or nonmultiplexed buses

Intel or Motorola formats

Supports polled or interrupt environments

Software access to device ID and silicon revision

Software reset supported

– Automatic clear on power-up

Hardware reset pin

The DS2156 is compliant with the following standards:

ANSI:

T1.403-1995, T1.231–1993, T1.408

AT&T:

TR54016, TR62411

ITU:

G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161

ITU-T:

Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer

Specification

ETSI:

ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4

Japanese:

JTG.703, JTI.431, JJ-20.11 (CMI Coding Only)

ATM Forum:

“DS1 Physical Layer Specification,” af-phy-0016.000, September 1994

ATM Forum:

“E1 Physical Layer Specification,” af-phy-0064.000, September 1996

ATM Forum:

“UTOPIA Level 2 Specification,” Version 1.0, af-phy-0039.000, June 1995

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