DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

DS2156

2.1 Block Diagram

Figure 2-1 shows a simplified block diagram featuring the major components of the DS2156. Details are

shown in subsequent figures. About 30 device pins have dual functions depending on the selection of the

backplane, UTOPIA, or TDM. Some of the block diagrams depict a configuration based on the state of

the backplane selection. The block diagram is divided into three functional blocks: LIU, FRAMER, and

BACKPLANE INTERFACE.

Figure 2-1. Block Diagram

CLOCK

CLOCK

ADAPTER

EXTERNAL ACCESS

TO RECEIVE SIGNALS

(TDM BACKPLANE ONLY)

HDB3 / B8ZS

RX

MUX

SYNC

LIU

SINGALING

ALARM DET

HDLCs

TX

LIU

MUX

LIU

EXTERNAL ACCESS

TO TRANSMIT SIGNALS

(TDM BACKPLANE ONLY)

FRAMER

SINGALING

ALARM GEN

HDLCs

CRC GEN

HDB3 / B8ZS

FRAMER

JTAG HOST INTERFACE ESIB

BACKPLANE

CLOCK SYNTH

BACKPLANE

INTERFACE

CIRCUIT

UTOPIA

or

TDM

BACKPLANE

INTERFACE

DS2156

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