DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

Figure 2-6. Backplane Interface (UTOPIA Bus Enabled)

DS2156

RCLK

RCHCLK

DATA

SYNC

TCHCLK

DATA

SYNC

TCLK

RSYNC

RDATA

RCLK

RECEIVE

FRAMER

INTERFACE

LOOPBACK

CONTROL

SCRAMBLING

& RATE

DECOUPLING

CELL

STORAGE

FIFO

RECEIVE

UTOPIA BUS

INTERFACE

UR-ENB

UR-SOC

UR-CLK

UR-CLAV0

5 UR-ADDR0 TO

UR-ADDR4

8 UR-DATA0 TO

UR-DATA7

DATA TRANSMIT

FRAMER

INTERFACE

CONTROL

SCRAMBLING

& RATE

DECOUPLING

CELL

STORAGE

FIFO

TRANSMIT

UTOPIA BUS

INTERFACE

UT-ENB

UT-SOC

UT-CLK

UT-CLAV0

UT-2CLAV0

5 UT-ADDR0 TO

UT-ADDR4

8 UT-DATA0 TO

UT-DATA7

TCLK

UT-UTDO

TSYNC

TDATA

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