78Q2133_F Просмотр технического описания (PDF) - Unspecified
Номер в каталоге
Компоненты Описание
производитель
78Q2133_F Datasheet PDF : 42 Pages
| |||
78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
MR16: Vendor Specific Register (continued)
BIT SYMBOL TYPE DEFAULT DESCRIPTION
16.1 PCSBP R/W
0
PCS Bypass Mode: When set, the 100Base-TX PCS and scrambling/
descrambling functions are bypassed. Scrambled 5-bit code groups for
transmission are applied to the TX_ER, TXD3-0 pins and received on
the RX_ER, RXD3-0 pins. The RX_DV and TX_EN signals are not
valid in this mode. PCSBP mode is valid only when 100Base-TX mode
is enabled and auto-negotiation is disabled.
16.0 RXCC R/W
0
Receive Clock Control: This function is valid only in 100Base-TX
mode. When set to ‘1’, the RX_CLK signal will be held low when there
is no data being received (to save power). The RX_CLK signal will
restart 1 clock cycle before the assertion of RX_DV and will be shut off
64 clock cycles after RX_DV goes low. RXCC is disabled when
loopback mode is enabled (MR0.14 is high). This bit should be kept at
logic zero when PCS Bypass mode is used.
MR17: Interrupt Control/Status Register
The Interrupt Control/Status Register provides the means for controlling and observing the events, which trigger
an interrupt on the INTR pin. This register can also be used in a polling mode via the MII Serial Interface as a
means to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are
each set to logic one based upon an event. These bits are cleared after the register is read. Bits 8 through 15 of
this register, when set to logic one, enable their corresponding bit in the lower byte to signal an interrupt on the
INTR pin. The assertion level of this interrupt signal output on the INTR pin can be set via the MR16.14 (INPOL)
bit.
BIT
17.15
17.14
17.13
17.12
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
SYMBOL
JABBER_IE
RXER_IE
PRX_IE
PDF_IE
LP-ACK_IE
LS-CHG_IE
RFAULT_IE
ANEG-
COMP_IE
JAB_INT
RXER_INT
PRX_INT
PDF_INT
TYPE DEFAULT DESCRIPTION
R/W
0
Jabber Interrupt Enable
R/W
0
Receive Error Interrupt Enable
R/W
0
Page Received Interrupt Enable
R/W
0
Parallel Detect Fault Interrupt Enable
R/W
0
Link Partner Acknowledge Interrupt Enable
R/W
0
Link Status Change Interrupt Enable
R/W
0
Remote Fault Interrupt Enable
R/W
0
Auto-Negotiation Complete Interrupt Enable
RC
0
Jabber Interrupt: This bit is set high when a Jabber event is
detected by the 10Base-T circuitry.
RC
0
Receive Error Interrupt: This bit is set high when the RX_ER
signal transitions high.
RC
0
Page Received Interrupt: This bit is set high when a new page
has been received from the link partner during auto-negotiation.
RC
0
Parallel Detect Fault Interrupt: This bit is set high by the auto-
negotiation logic when a parallel detect fault condition is
indicated.
Page: 18 of 42
© 2009 Teridian Semiconductor Corporation
Rev 1.5
Share Link: 