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78Q2133_F

MicroPHY™ 10/100BASE-TX Transceiver

Unspecified 

78Q2123/78Q2133 MicroPHY™

10/100BASE-TX Transceiver

MR1: Status Register (continued)

BIT SYMBOL TYPE DEFAULT DESCRIPTION

1.4 RFAULT RC

0

Remote Fault: A logic one indicates that a remote fault condition has

been detected and it remains set until it is cleared. This bit can only

be cleared by reading this register (MR1) via the management

interface.

1.3 ANEGA

R

(1) Auto-Negotiation Ability: When set, this bit indicates the device’s

ability to perform Auto-Negotiation. The value of this bit is determined

by the ANEGEN bit (MR0.12).

1.2

LINK

R

0

Link Status: A logic one indicates that a valid link has been

established. If the link status should transition from an OK status to a

NOT-OK status, this bit will become cleared and remains cleared until

it is read.

1.1

JAB

RC

0

Jabber Detect: In 10Base-T mode, this bit is set during a jabber

event. After a jabber event, the bit remains set until cleared by a read

operation.

1.0

EXTD

R

1

Extended Capability: Reads ’1’ to indicate the 78Q2123/78Q2133

provide an extended register set (MR2 and beyond).

MR2: PHY Identifier Register 1

BIT

2.15:0

SYMBOL

OUI

[23:6]

TYPE

R

VALUE

000Eh

DESCRIPTION

Organizationally Unique Identifier: This value is 00-C0-39 for

TERIDIAN Semiconductor Corporation. This register contains the first

16-bits of the identifier.

MR3: PHY Identifier Register 2

BIT

3.15:10

3.9:4

SYMBOL

OUI

[5:0]

MN

TYPE

R

R

3.3:0

RN

R

VALUE

1Ch

23h

07h

DESCRIPTION

Organizationally Unique Identifier: Remaining 6 bits of the OUI.

Model Number: The last 2 digits of the model number 78Q2123 are

encoded into the 6 bits for both 78Q2123 and 78Q2133.

Revision Number: The value ‘0111’ corresponds to the seventh

revision of the silicon.

Page: 14 of 42

© 2009 Teridian Semiconductor Corporation

Rev 1.5

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