HFA3841 Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

HFA3841

Wireless LAN Medium Access Controller

Intersil 

Preliminary - HFA3841

Waveforms (Continued)

OSC

44MHz

23ns

MCLK

(INTERNAL)

QCLK

(INTERNAL)

10ns (NOTE 12)

14.67MHz

68.2ns

10ns

(NOTE 12)

10ns (NOTE 12)

MCLKOUT

ADDRESS,

RAMCS_

MOE_

MD0-15

READ DATA

11.5ns

17ns

17ns

24ns

VALID DATA AT MDIN

tH≥0

MWEH/L_

MD0-15

WRITE DATA

13ns

16ns

20ns

VALID DATA

tH≥0

MBUS READ CYCLE

MBUS WRITE CYCLE

NOTES:

11. 14.67MHz requires an odd divisor in the prescaler. Note that both edges of OSC are used to create MCLK and QCLK, thus a deviation from

50% duty cycle in OSC will result in corresponding changes in MBUS timing.

12. Timing delays between OSC and internal clocks are shown for information purposes only.

FIGURE 3. MBUS MEMORY TIMING - 14.67MHz MCLK

MCLK

EMA [15:0]

EMCSxN

EMOEN

EMWRN

EMD [15:0]

11

tD1

tD2

tD1

tD3

tD4

tD5

tS1

tH1

tD6

FIGURE 4.

Share Link: