HFA3841 Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

HFA3841

Wireless LAN Medium Access Controller

Intersil 

Preliminary - HFA3841

The HFA3841 was designed to implement 16-bit wide

memory by using two 8-bit RAM chips. The HFA3841

provides high and low write enable signals (MWEH_ and

MWEL_), and a single output enable (MOE_). This allows a

direct connection, enabling a pair of 8-bit SRAMs to function

as a 16-bit device. MA0 functions as Address 0 for 8-bit

access (such as Flash), and as MWEH (High Byte Write

Enable) for 16-bit access (such as SRAM), since address bit

0 is not used for 16-bit accesses.

Some single chip 16-bit SRAMs use an alternate connection

scheme with five pins: a Chip Select, an Output Enable, a

single Write Enable, and Upper and Lower byte enables,

which control both read and write cycles. Thus, external

logic is required to generate the required signals.

See Application Note AN9844, "HFA3841 to PRISMII

Connections" for important information regarding the

connection of these types of 16-bit SRAM chips to the

HFA3841.

Host Interface

PC Card Physical Interface

The Host interface is compatible to the PC Card 95 Standard

(PCMCIA v2.1). The HFA3841 Host Interface pins connect

directly to the correspondingly named pins on the PC Card

connector with no external components (other than

resistors) required. The HFA3841 operates as an I/O card

using less than 64 octet locations. Reads and writes to

internal registers and buffer memory are performed by I/O

accesses. Attribute memory (256 octets) is provided for the

CIS table which is located in external memory. Common

memory is not used.

The following describes specific features of various pins:

HA[9:0]

Decoding of the system address space is performed by the

HCEx-. During I/O accesses HA[5:0] decode the register.

HA[9:6] are ignored when the internal HAMASK register is

set to the defaults used by the standard firmware. During

attribute memory accesses HA[9:1] are used.

HD[15:0]

The host interface is primarily designed for word accesses,

although all byte access modes are fully supported. See

HCE1-, HCE2- for a further description. Note that attribute

memory is specified for and operates with even bytes

accesses only.

HCE1-, HCE2-

The PC Card cycle type and width are controlled with the CE

signals. Word and Byte wide accesses are supported, using

the combinations of HCE1-, HCE2-, and HA0 as specified in

the PC Card standard.

HWE-, HOE-

HOE- and HWE- are only used to access attribute memory.

Common Memory, as specified in the PC Card standard, is

not used in the HFA3841. HOE- is the strobe that enables an

attribute memory read cycle. HWE- is the corresponding

strobe for the attribute memory write cycle. The attribute

space contains the Card Information Structure (CIS) as well

as the Function Configuration Registers (FCR).

HIORD-, HIOWR-

HIORD- and HIOWR- are the enabling strobes for register

access cycles to the HFA3841. These cycles can only be

performed once the initialization procedure is complete and

the HFA3841 has been put into IO mode.

HREG-

This signal must be asserted for I/O or attribute cycles. A

cycle with HREG- unasserted will be ignored as the

HFA3841 does not support common memory.

HINPACK-

This signal is asserted by the HFA3841 whenever a valid I/O

read cycle takes place. A valid cycle is when HCE1-, HCE2-,

HREG-, and HIORD- are asserted, once the initialization

procedure is complete.

HWAIT-

Wait states are inserted in accesses using HWAIT-. The host

interface synchronizes all PC Card cycles to the internal

HFA3841 clock. The following wait states should be

expected:

Direct Read or Write to Hardware Register

• 1/2 to 1 MCLK assertion of HWAIT- for internal

synchronization.

Write to Memory Mapped Register, Buffer Access Path,

or Attribute Space (Post-Write)

• The data required for the write cycle will be latched and

therefore only the synchronizing wait state will occur.

• Until the queued cycle has actually written to the memory,

any subsequent access by the Host will result in a WAIT.

Read to Attribute Space and Memory Mapped Registers

• WAIT will assert until the memory arbitration and access

have completed.

Buffer Access Paths, BAP0 and BAP1

• An internal Pre-Read cycle to memory is initiated by a

host Buffer Read cycle, after the internal address pointer

has auto-incremented. If the next host cycle is a read to

the same buffer, the data will be available without a

memory arbitration delay.

• A single register holds the pre-read data. Thus, any read

access to any other memory-mapped register (or the other

17

Share Link: