UT1750AR12WCC Просмотр технического описания (PDF) - Aeroflex UTMC

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UT1750AR12WCC

RISC Microprocessor

Aeroflex UTMC 

GENERAL OPERATION

The UT1750AR can operate in two modes. The first operating

mode is the Reduced Instruction Set Computer (RISC) mode;

the second is the MIL-STD-1750A Instruction Set Architecture

(ISA) emulation mode. The mode-select input pin (M1750)

determines the UT1750AR’s operating mode. M1750 must be

tied high to enable the MIL-STD-1750A ISAemulation mode

of operation; otherwise, an internal pull-down resistor pulls

M1750 low, selecting the RISC mode.

The UT1750AR has a Harvard architecture when it operates in

the RISC mode (M1750 = 0). A processor with a Harvard

architecture has two sets of address and data busses; one set

interfaces with instruction memory and the other set interfaces

with operand memory. This architecture allows the UT1750AR

to perform overlapping instruction fetch-and-execute bus cycles

that enhance processor throughput.

The UT1750AR’s reduced instruction set consists of 30 separate

instructions. The UT1750AR executes most of these

instructions in two clock cycles providing fast execution of

RISC-coded programs. All the UT1750AR’s processing

capabilities in the RISC mode are available to the system

programmer by using the companion RISC Assembler

(RASM)/Linker (RLNK), RISC Interactive Software Simulator

(IRSIM), and hardware development debug tools.

In the MIL-STD-1750A mode of operation (M1750 = 1), the

UT1750AR has a Von Neumann architecture. A processor with

a Von Neumann architecture has a common set of address and

data busses that make instructions and operand data available

to the processor.

The UT1750AR emulates the MIL-STD-1750A instruction set

when it has a specially programmed set of RISC PROMs. These

PROMs contain RISC-coded macros that correspond to each

MIL-STD-1750 instruction. When the UT1750AR fetches a

1750 instruction from memory, it decodes this instruction’s

opcode and generates an address for the RISC PROMs. This

address points to a RISC macro that, when executed, performs

the operation the 1750 instruction requires.

The high execution rate of the UT1750AR’s native RISC

language is also available when the UT1750AR is in the MIL-

STD-1750 mode of operation by using the MIL-STD-1750

Built-in-Function (BIF) opcode. The system designer can

develop a RISC macro for a specific function, such as power-

on self-test routines, built-in-test routines, signal-processing

routines, or any routine that requires real-time processing. The

UT1750AR executes this function when it encounters the BIF

in the MIL-STD-1750 program flow.

The RISC Mode of Operation

The configuration for the UT1750AR in the RISC mode of

operation is shown in figure 4. RISC is the default mode of

operation for the UT1750AR since the M1750 input is tied to

an internal pull-down resistor.

When the UT1750AR operates in the RISC mode, the system

designer stores the executable RISC program in RISC memory.

The UTMC RISC Assembler generates this executable RISC

program. All 20 of the RISC address lines can access a user-

defined program in RISC memory. This means the maximum

length of any RISC program is 1 mega- word.

Although the executable RISC program is all that is stored in

RISC memory, two RISC instructions allow the programmer to

manipulate the data in RISC memory. These instructions are the

Load Register from (RISC) Instruction Memory (LRI) and the

Store Register to (RISC) Instruction Memory (STRI).

When operating in the RISC mode, the UT1750AR first

generates an address on the RISC address bus for the instruction

it stores in the Primary Instruction Register (PIR). After the

UT1750AR stores the RISC instruction in the PIR, the

UT1750AR begins executing the instruction in the Instruction

Register (IR). If the present instruction in the IR requires only

internal processing, the UT1750AR does not exercise the

Operand Address and data busses. If, on the other hand, the

instruction in the IR requires some type of Operand Data, the

UT1750AR begins an Operand bus arbitration cycle midway

through the next processor clock cycle.

The Operand bus arbitration cycle begins with the UT1750AR

asserting the Bus Request (BRQ) signal. The UT1750AR

samples the Bus Grant (BGNT) and the Bus Busy (BUSY)

signals on every falling edge of the processor clock. When the

UT1750AR detects that the previous bus controller has

relinquished control of the bus, the UT1750AR generates the

Bus Grant Acknowledge (BGACK) signal signifying that it has

taken control of the bus.

After the UT1750AR has taken control of the bus, it generates

the Operand address and data. The Address Strobe (AS) and

Data Strobe (DS) signals indicate when the Operand address

and data are valid. If the UT1750AR is interfacing to slow

memory or other peripheral devices that require long memory-

access times, the Data Transfer Acknowledge (DTACK) signal

extends the memory cycle time. By holding off the assertion of

DTACK, the slow memory device lengthens the memory cycle

until it can provide data for the UT1750AR.

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