UT1750AR12WCC Просмотр технического описания (PDF) - Aeroflex UTMC

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UT1750AR12WCC

RISC Microprocessor

Aeroflex UTMC 

RISC INSTRUCTION MEMORY

CAN ONLY BE ACCESSED

BY THE UT1750AR

RISC

MEMORY

1M X 16

(MAX)

BRQ

BGNT

BUSY

16

RISC BGACK

DATA

20

RISC

ADD OP ADD

OE OP DATA

WE CONTROL

4

BUS

ARBITER

DMA

DEVICE

#1

1553

I/F

16

16

6

DMA

DEVICE

#2

INTERNALLY

PULLED LOW

USER-

DEFINED

8

SYSTEM

INTERRUPTS

M1750

UT1750AR

UART

I/F

GENERAL

PURPOSE

MEMORY

I/O

DEVICE #1

X

C

V

SERIAL I/O

R

I/O

DEVICE #2

Figure 4. The UT1750AR in the RISC Mode of Operation

All user-definable interrupts are available when the UT1750AR

is operating as a RISC. In addition, the system programmer can

read or write to virtually all of the UT1750AR’s internal

registers, either general purpose or specialized, when the

UT1750AR is in the RISC mode by using the Internal I/O

command (INR) or the Output Register command (OTR),

respectively.

The 1750A Mode of Operation

The configuration for the UT1750AR in the MIL-STD-1750A

mode of operation is shown in figure 5. The UT1750AR enters

the 1750 mode of operation when the mode input, M1750, is

pulled high.

The functional operation of the UT1750AR in the MIL-STD-

1750 mode is similar to the RISC mode of operation, although

it has two important differences. The first difference is that when

the system designer selects the MIL-STD-1750 mode, the

UT1750AR requires a specific set of RISC PROMs specially

programmed to allow the UT1750AR to emulate the 1750 ISA.

This special set of RISC PROMs contains a set of RISC-coded

macros that allow the UT1750AR to serve as a full-feature MIL-

STD-1750A microprocessor. In this respect, the RISC PROMs

hold external microcode, or “Mili”-code. This “Mili”-code tells

the UT1750AR how to function as a 1750 processor and, if

necessary, the user can change the “Mili”-code if the application

requires additional capability for real-time processing.

The second difference between the operation of the UT1750AR

in the 1750 mode and the RISC mode is that in the 1750 mode

the RISC address bus is limited to 16 address lines or 64K words

instead of the UT1750AR’s 20-bit RISC address bus in the RISC

mode. When in the 1750 mode, the UT1750AR uses the four

most significant bits of the RISC address bus for output

discretes. The output discrete that replaces the most significant

address bit (RA19) is a dedicated chip select.

12

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