ST18D952 Просмотр технического описания (PDF) - STMicroelectronics
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ST18D952 Datasheet PDF : 67 Pages
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ST18952
5.2 Direct bus extension
Direct extension for I-memory
The internal program memory is used from address 0 to 32767 (32 K). Note, no detection is
provided when an internal space is declared as an external one for the BSU.
The I-bus direct transfer enable signal (IDT_EN) determines whether an access is made
directly to external memory or via the BSU. If reset occurs with the MODE signal set to ‘1’
(select reset address to xFC00), then
• if IDT_EN input = 0: access to external memory is through the BSU
• if IDT_EN input = 1: access to direct external memory space
IAE/IBSE/IRDE/IWRE are always driven except in the case of an external HOLD request.
Note: an external coprocessor will work only when executing program in the external space.
IDE bus is an output only when a direct external write is detected. IDE bus is an input in the
case of:
• an external memory read
• DMA (write) transfers between an external peripheral and internal memory
Direct extension for X-memory
The internal X memory is used from address 0 to 8703 (8.5 K). It is extended with external
memory from address 8704 (8.5K) to 65535 (64K) with the XE bus extension.
The direct extension is managed by the bus switch unit. When the EN_X bit of the BSU XER
register (see ”XER0/1: X-memory space control registers” on page 20) is set to ‘0’, it generates
only software wait-states and access is direct. If the EN_X bit is set to ‘1’, data goes via the
BSU.
X extension and bus switch share the same I/O’s.
Direct extension for Y-memory
The internal Y memory is used from address 0 to 8703 (8.5 K). It is extended with external
memory from address 8704 (8.5 K) to 65535 (64 K) with the YE bus extension.
Address 0 to 256 of the Y space are reserved for memory mapped registers.
Note: The BSU and X direct extension share the same I/O, therefore extension of IE through
the BSU is not possible when direct extension is selected for X/Y. Some combinations of the
EN_I, EN_X and EN_Y bits of the BSU control registers IER/XER/YER are not allowed, as
shown in Table 5.1 below.
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