ADSP-21065L Просмотр технического описания (PDF) - Analog Devices
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ADSP-21065L Datasheet PDF : 44 Pages
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ADSP-21065L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
Parameter
Timing Requirements:
tSSDATI
tHSDATI
tDAAK
tSACKC
tHACK
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address, MSx, SW, BMS1, 2
ACK Setup Before CLKIN1
ACK Hold After CLKIN
Min
0.25 + 2 DT
4.0 – 2 DT
2.75 + 4 DT
2.0 – 4 DT
Max
Unit
ns
ns
24.0 + 30 DT + W ns
ns
ns
Switching Characteristics:
tDADRO
tHADRO
tDRDO
tDWRO
tDRWL
Address, MSx, BMS, SW Delay After CLKIN1
Address, MSx, BMS, SW Hold After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
tDDATO
Data Delay After CLKIN
tDATTR
Data Disable After CLKIN3
tDBM
BMSTR Delay After CLKIN
tHBM
BMSTR Hold After CLKIN
0.5 – 2 DT
0.5 – 2 DT
0.0 – 3 DT
7.5 + 4 DT
1.0 – 2 DT
–4.0
7.0 – 2 DT
ns
ns
6.0 – 2 DT
ns
6.0 – 3 DT
ns
11.75 + 4 DT
ns
22.0 + 10 DT
ns
7.0 – 2 DT
ns
3.0
ns
ns
W = (number of wait states specified in WAIT register) ¥ tCK.
NOTES
1Data Hold: User must meet tHDA or tHDRH or synchronous specification tHDATI. See system hold time calculation under test conditions for the calculation of hold
times given capacitive and dc loads.
2ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t SACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
–18–
REV. C
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