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ADSP-21065L

DSP Microcomputer

Analog Devices 

ADSP-21065L

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.

These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching

characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these

timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin

timing requirements as described in the note below.

Parameter

Timing Requirements:

tDAAK

tDSAK

ACK Delay from Address1, 2

ACK Delay from WR Low1

Min

Max

Unit

24.0 + 30 DT + W ns

19.5 + 24 DT + W ns

Switching Characteristics:

tDAWH

Address, Selects to WR Deasserted2

tDAWL

Address, Selects to WR Low2

tWW

tDDWH

WR Pulsewidth

Data Setup Before WR High

tDWHA

tDATRWH

Address Hold After WR Deasserted

Data Disable After WR Deasserted3

tWWR

tWRDGL

WR High to WR, RD Low

WR High to DMAGx Low

tDDWR

Data Disable Before WR or RD Low

tWDE

WR Low to Data Enabled

29.0 + 31 DT + W

ns

3.5 + 6 DT

ns

24.5 + 25 DT + W

ns

15.5 + 19 DT + W

ns

0.0 + 1 DT + H

ns

1.0 + 1 DT + H

4.0 + 1 DT + H

ns

4.5 + 7 DT + H

ns

11.0 + 13 DT + H

ns

3.5 + 6 DT + I

ns

4.5 + 6 DT

ns

W = (number of wait states specified in WAIT register) ¥ tCK.

H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOTES

1ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be

valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and

subsequent cycles of a wait stated external memory access, synchronous specifications t SACKC and tHACKC must be met for wait state modes External, Either, or Both

(Both, after internal wait states have completed).

2The falling edge of MSx, SW, and BMS is referenced.

3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx , SW

BMS

WR

DATA

ACK

RD

t DAWL

t DAWH

t WW

t WDE

t DAAK

t DSAK

t DDWH

t DWHA

t DATRWH

t WWR

t DDWR

DMAG

Figure 12. Memory Write—Bus Master

t WRDGL

REV. C

–17–

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