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ADSP-21065L

DSP Microcomputer

Analog Devices 

ADSP-21065L

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.

These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching

characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these

timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin

timing requirements as described in the note below.

Parameter

Timing Requirements:

tDAD

tDRLD

Address, Selects Delay to Data Valid1, 2

RD Low to Data Valid1

tHDA

tHDRH

tDAAK

tDSAK

Data Hold from Address Selects3

Data Hold from RD High3

ACK Delay from Address, Selects2, 3

ACK Delay from RD Low3

Min

Max

Unit

28.0 + 32 DT + W ns

24.0 + 26 DT + W ns

0.0

ns

0.0

ns

24.0 + 30 DT + W ns

19.5 + 24 DT + W ns

Switching Characteristics:

tDRHA

Address, Selects Hold After RD High

–1.0 + H

ns

tDARL

Address, Selects to RD Low2

3.0 + 6 DT

ns

tRW

RD Pulsewidth

25.0 + 26 DT + W

ns

tRWR

RD High to WR, RD Low

4.5 + 6 DT + HI

ns

tRDGL

RD High to DMAGx Low

11.0 +12 DT + HI

ns

W = (number of wait states specified in WAIT register) ¥ tCK.

HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

NOTES

1Data Delay/Setup: User must meet tDAD or to tDRLD or synchronous specification tSSDATI.

2The falling edge of MSx, SW, BMS, are referenced.

3ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be

valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and

subsequent cycles of a wait stated external memory access, synchronous specifications t SACKC and tHACKC must be met for wait state modes External, Either, or Both

(Both, after internal wait states have completed).

ADDRESS

MSx , SW

BMS

RD

DATA

ACK

WR

t DARL

t RW

t DRLD

t DAD

t DAAK

t DSAK

t DRHA

t HDA

t HDRH

t RWR

DMAG

t RDGL

Figure 11. Memory Read—Bus Master

–16–

REV. C

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