M4A5-384/128-5SAC Просмотр технического описания (PDF) - Lattice Semiconductor
Номер в каталоге
Компоненты Описание
производитель
M4A5-384/128-5SAC
Lattice Semiconductor
M4A5-384/128-5SAC Datasheet PDF : 63 Pages
| |||
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input Register Delays with ZHT Option:
tSIRZ Input register setup time - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
tHIRZ Input register hold time - ZHT
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
Input Latch Delays with ZHT Option:
tSILZ Input latch setup time - ZHT
tHILZ Input latch hold time - ZHT
tPDIL Transparent input latch to internal
Zi feedback - ZHT
Output Delays:
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0 ns
tBUF Output buffer delay
tSLW Slow slew rate delay adder
tEA Output enable time
tER Output disable time
Power Delay:
1.5
1.5
1.8
2.0
2.5
3.0
3.0
3.0 ns
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5 ns
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0 ns
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0 ns
tPL Power-down mode delay adder
Reset and Preset Delays:
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5 ns
tSRi
Asynchronous reset or preset to internal
register output
7.5
7.7
8.0
8.0
9.5
11.0
13.0
16.0 ns
tSR
Asynchronous reset or preset to register
output
9.0
9.2
10.0
10.0
12.0
14.0
16.0
19.0 ns
Asynchronous reset and preset register
tSRR recovery time
7.0
7.0
7.5
7.5
8.0
8.0
10.0
15.0
ns
tSRW Asynchronous reset or preset width
7.0
7.0
8.0
8.0
10.0
10.0
12.0
15.0
ns
Clock/LE Width:
tWLS Global clock width low
tWHS Global clock width high
tWLA Product term clock width low
tWHA Product term clock width high
Global gate width low (for low
tGWS transparent) or high (for high
transparent)
2.0
2.0
2.5
2.5
3.0
4.0
5.0
6.0
ns
2.0
2.0
2.5
2.5
3.0
4.0
5.0
6.0
ns
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
Product term gate width low (for low
tGWA transparent) or high (for high
transparent)
4.0
4.0
4.5
4.5
5.0
5.0
6.0
9.0
ns
tWIRL Input register clock width low
tWIRH Input register clock width high
tWIL Input latch gate width
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
ispMACH 4A Family
39
Share Link: