M4A5-384/128-5SAC Просмотр технического описания (PDF) - Lattice Semiconductor

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M4A5-384/128-5SAC

ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

Lattice Semiconductor 

ICC vs. FREQUENCY

These curves represent the typical power consumption for a particular device at system frequency. The

selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every

macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are

optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is

placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed

in a common PAL block and set to lowest power.

400

VCC = 5 V or 3.3 V, TA = 25º C

M4A-512/160

350

M4A-384/160

M4A-256/160

300

250

M4A-256/128

200

M4A-192/96

150

M4A-96/48

M4A-128/64

100

M4A-64/64

M4A-64/32

50

M4A-32/32

0

Frequency (MHz)

Figure 19. ispMACH 4A ICC Curves at High Speed Mode

250

VCC = 5 V or 3.3 V, TA = 25º C

M4A-512/160

M4A-384/160

200

M4A-256/160

150

M4A-256/128

M4A-192/96

100

M4A-96/48

M4A-128/64

M4A-64/64

50

M4A-64/32

M4A-32/32

0

Frequency (MHz)

Figure 20. ispMACH 4A ICC Curves at Low Power Mode

ispMACH 4A Family

41

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