L9826_02 Просмотр технического описания (PDF) - STMicroelectronics
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L9826_02 Datasheet PDF : 12 Pages
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L9826
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
Outputs short circuit protection
ISBC Overcurrent shutoff threshold OUT3 ... OUT8
0.45
1.1
A
ILIM Short circuit current limitation
tSCB Delay shutdown
OUT1; OUT2
for output 3 ... 8; IOUT ≤ 1/2 ISCB
0.5
1,0
A
0.2
3,0
12
µs
Diagnostics
VDG Diagnostic threshold voltage
0.32·V
CC
0.4·VC V
C
IOL Open load detection sink
current
Vout = VDG
20
100
µA
tdf Diagnostic detection filter time
for output 1 & 2 on each
diagnostic condition
15
50
µs
Outputs timing
tdon1
Turn ON delay of OUT 1 and 2
NON1, 2 = 50% to VOUT = 0,9·Vbat
NCS = 50% to VOUT = 0,9·Vbat
5
µs
tdon2 Turn ON delay of OUT 3 to 8
NCS = 50% to VOUT = 0,9·Vbat
10
µs
tdoff Turn OFF delay of OUT 1 to 8 NCS = 50% to VOUT = 0,1·Vbat
NON1, 2 = 50% to VOUT = 0,1·Vbat
10
µs
dUon1/dt Turn ON voltage slew-rate
For output 3 to 8; 90% to 30% of
0.7
Vbat; RL = 500Ω; Vbat = 16V
3.5 V/µs
dUon2/dt Turn ON voltage slew-rate
For output 1 and 2; 90% to 30% of
2
Vbat; RL = 500Ω; Vbat = 16V
10 V/µs
dUoff1/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 90% of
2
Vbat; RL = 500Ω; Vbat = 16V
10 V/µs
dUoff2/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 80% of
2
Vbat; RL = 500Ω; Vbat = 0.9 · Vclp
15 V/µs
Serial diagnostic link (Load capacitor at SDO = 100pF)
fclk Clock frequency
50% duty cycle
3
MHz
tclh Minimum time CLK = HIGH
160
ns
tcll Minimum time CLK = LOW
160
ns
tpcld Propagation delay
CLK to data at SDO valid
4,9V ≤ VCC ≤ 5,1V
100
ns
tcsdv NCS = LOW to data at SDO
active
100
ns
tsclch CLK low before NCS low
Setup time CLK to NCS change H/L 100
ns
5/12
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