DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

L9826_02 Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге
Компоненты Описание
производитель
L9826_02 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
L9826
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
thclcl CLK change L/H after NCS =
low
100
ns
tscld SDI input setup time
CLK change H/L after SDI data
20
ns
valid
thcld SDI input hold time
SDI data hold after CLK change H/L
20
ns
tsclcl CLK low before NCS high
150
ns
thclch CLK high after NCS high
150
ns
tpchdz NCS L/H to output data float
100
ns
NCS pulse filter time
Multiple of 8 CLK cycles inside
NCS period
FUNCTIONAL DESCRIPTION
General
The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using
the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power
outputs features voltage clamping function for flyback current recirculation and are protected against short cir-
cuit to Vbat.
The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and ther-
mal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to GND in switch-off condition
for all outputs. The outputs status can be read out via the serial interface.
The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes
signal.
Output Stages Control
Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1
and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These
inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open.
The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1.
The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every
falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.
6/12

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]