ISPXPLD5512MX Просмотр технического описания (PDF) - Lattice Semiconductor

Номер в каталоге

Компоненты Описание

производитель

ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Pseudo Dual-Port SRAM Mode

In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and

write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the

MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.

Write data, write address, chip select and write enable signals are always synchronous (registered). The read data

and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the

same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both

read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for

the various registers.

Figure 10. Pseudo Dual-Port SRAM Block Diagram

CLK0

CLK1

CLK2

CLK3

RESET

Read Address

(RAD[0:8-13])

Write Address

(WAD[0:8-13])

Read Data

(RD[0:0-15])

68 Inputs

From

Routing

Write Data

(WD[0:0,1,3,7,15,31])

16,384 bit

Pseudo

Write Enable (WE)

Write Clock (WCLK)

‘ ‘ Dual

Port

SRAM

Write Chip Sel (WCS[0,1]) Array

Write Clk Enable (WCEN)

Read Clk Enable (RCEN)

Read Clock (RCLK)

Reset (RST)

Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode

Register

Input

Clock

Write Address, Write

Data, Write Enable,

Clock Enable

and Write Chip Select

Reset

Clock

Read Data and Read Clock Enable

Address

Reset

Source

WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can

be inverted if desired.

WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can

be inverted if desired.

Created by the logical OR of the global reset signal and RST. RST may have

inversion if desired.

RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be

inverted if desired.

RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can

be inverted if desired.

Created by the logical OR of the global reset signal and RST. RST may have

inversion if desired.

11

Share Link: