ISPXPLD5512MX Просмотр технического описания (PDF) - Lattice Semiconductor

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ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Single-Port SRAM Mode

In Single-Port SRAM Mode the multi-function array is configured as a single-port SRAM. In this mode one ports

accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 11 shows

the block diagram of the single-port SRAM.

Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-

nals can be synchronous or asynchronous. Reset is asynchronous. All signals share a common clock, clock

enable, and reset. Table 7 shows the possible sources for the clock, clock enable and reset signals.

Figure 11. Single-Port SRAM Block Diagram

CLK0

CLK1

CLK2

CLK3

RESET

68 Inputs

from

Routing

Read/Write Address

(AD[0-8:13])

Write Data

(DI[0-0,1,3,7,15,31])

Write/Read (WR)

Clock (CLK)

Chip Select (CS0,1)

Clk Enable (CEN)

Reset (RST)

16,384-Bit

‘ ‘SRAM

Array

Read Data

(DO[0-0,31])

Table 7. Register Clock, Clock Enable, and Reset in Single-Port SRAM Mode

Register

Address, Write Data,

Read Data, Read/

Write, and Chip

Select

Input

Clock

Clock Enable

Reset

Source

CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can

be inverted if required.

CEN or one of the global clocks (CLK1 - CLK 2). Each of these signals can

be inverted if required.

Created by the logical OR of the global reset signal and RST. RST is routed

by the multifunction array from GRP, with inversion if desired.

12

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