ISPXPLD5512MX Просмотр технического описания (PDF) - Lattice Semiconductor

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ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

Figure 15. PLL Block Diagram

CLK_IN

PLL_RST

Input Clock

(M) Divider

Programable

Delay

VCO

and

Phase

Detector

ispXPLD 5000MX Family Data Sheet

Post-scalar

(V) Divider

CLK_OUT

Clock Net

PLL_LOCK

PLL_FBK

Feedback

Loop

(N) Divider

Figure 16. Connection of Optional PLL Inputs and Outputs

Secondary

Clock

(K) Divider

SEC_OUT

Clock Net

To GRP

PLL_LOCK

CLK_OUT

From Macrocell

To GRP

PLL_RST

To GRP

From Macrocell

I/O Pin*

I/O Pin*

To GRP

PLL_FBK

From Macrocell

I/O Pin*

*See pinout table for details

In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N

and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The

K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and

feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-

ing a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the out-

put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more

information on the PLL, please refer to Lattice technical note number TN1003, Lattice sysCLOCK PLL Usage

Guidelines.

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