HIP7010P Просмотр технического описания (PDF) - Intersil
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HIP7010P Datasheet PDF : 20 Pages
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HIP7010
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V
Input or Output Voltage
Pins with VDD Diode . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V
Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to +10.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates
Thermal Resistance
θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100oC/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120oC/W
Maximum Package Power Dissipation at +125oC
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW
Operating Temperature Range (TA) .
Storage Temperature Range (TSTG).
Junction Temperature . . . . . . . . . . . .
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- 40oC
- 65oC
......
to
to
..
+125oC
+150oC
+150oC
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -40oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8VDD) to VDD
Input Rise and Fall Time
CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max
CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited
Electrical Specifications TA = -40oC to +125oC, VDD = 5VDC ±10%, Unless Otherwise Specified
PARAMETERS
SYMBOL CONDITIONS
MIN
TYP
Supply Current
Operating Current
Power-Down Mode (Note 1)
Clock Stopped (Note 2)
Input High Voltage
IOP
CLK = 2.0 MHz
-
1.0
IPD
PD = 1
-
50
ISTOP CLK = VSS or VDD
-
5.0
CMOS Level (SIN, STAT, RDY, TEST)
VIH
Schmitt Trigger (RESET, CLK, VPWIN)
Input Low Voltage
0.7VDD
-
0.8VDD
-
CMOS Level (SIN, STAT, RDY, TEST)
VIL
Schmitt Trigger (RESET, CLK, VPWIN)
High Level Input Current
VSS
-
VSS
-
(CLK, VPWIN, RESET)
IIH
VIN = VDD
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-1
0.001
100
200
Low Level Input Current
(CLK, VPWIN, RESET)
IIL
VIN = VSS
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-1
- 0.001
-10
-0.01
Output High Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
Output Low Voltage
VOH
ILOAD = 0.8 mA
VDD-0.8
-
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
High Impedance Leakage Current
VOL
ILOAD = -1.6 mA
-
-
Three-State with Pull-Down (SCK, SOUT)
Schmitt Trigger Hysteresis Voltage
(RESET, CLK, VPWIN)
IOZ
VHYS
VOUT = VDD
VOUT = VSS
100
200
-10
0.2
0.5
NOTES:
1. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; CLK = 10MHz.
2. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; PD = 1.
MAX
5.0
150
50
VDD
VDD
0.3VDD
0.2VDD
1
500
1
10
-
0.4
500
10
2.0
UNITS
mA
µA
µA
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
V
3
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