HIP7010P Просмотр технического описания (PDF) - Intersil
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HIP7010P Datasheet PDF : 20 Pages
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HIP7010
Serial Interface Timing (See Figure 1- Figure 7) TA = -40oC to +125oC, VDD = 5VDC ±10%, Unless Otherwise Specified
NUMBER SYMBOL
PARAMETERS
MIN
TYP MAX UNITS
-
-
Operating Frequency
2
8
12
MHz
-
-
Input CLK Duty Cycle
40
50
60
%
(1)
tCYC SCK Cycle Time
(2)
tLEAD SACTIVE Lead Time
Before Status/Control Transfer
-
1.0
-
MHz
450
750
850
ns
Before Data Transfer
1150 1225 1300
ns
(3)
tLAG
SACTIVE Lag Time
After Status/Control Transfer
650
750
850
ns
After Data Transfer
1250 1300 1400
ns
(4)
tSCKH Clock (SCK) HIGH Time
450
500
550
ns
(5)
tSCKL Clock (SCK) LOW Time
450
500
550
ns
(6)
tDVSCK Required Data In Setup Time (SIN to SCK)
-
10
50
ns
(7)
tSCKDX Required Data In Hold Time (SIN after SCK)
-
-10
40
ns
(8)
tDZDA Data Active from High Impedance Delay (SACTIVE to SOUT Active) -10
10
-
ns
(9)
tDADZ Data Active to High Impedance Delay (SACTIVE to SOUT High
Impedance)
-
10
40
ns
(10)
tDVSCK Data Out Setup Time (SOUT to SCK)
(11)
tDXSCK Data Out Hold Time (SOUT after SCK)
(12)
tRISE Output Rise Time (0.3VDD to 0.7VDD, CL = 100pF)
(13)
tFALL Output Fall Time (0.7VDD to 0.3VDD, CL = 100pF)
(14)
tSTATH Required STAT Pulse Width
(15)
tRDYH Required RDY Pulse Width
tRESETL Required RESET Pulse Width
(16)
tSACTIVE SACTIVE Delay from RDY (IDLE = VSS)
SACTIVE Delay from STAT (FTU = 0)
375
475
-
ns
375
475
-
ns
15
75
150
ns
7
25
75
ns
-
20
75
ns
-
20
75
ns
-
20
75
ns
1150 1750 2450
ns
5
285
900
ns
(17)
tRDYSCK Required RDY Removal Time Prior to Last SCK for Short RDY
(18)
tSCKRDY Required RDY Hold Time after Last SCK for Long RDY
(19)
tREC Required SERIAL Recovery Time (Minimum Time after SACTIVE
Until Next RDY/STAT)
-
25
100
ns
-
0
100
ns
-
675
750
ns
fSLOW Slow clock detect frequency limit
20
80
200
KHz
NOTE:
1. All parameters are specifications of the HIP7010 component not of a system. Parameters specified as “Required” (i.e., tSTATH) refer to
the requirements of the HIP7010. If a “Required” pulse width is specified as 75ns maximum, that implies that 75ns is the maximum width
that any HIP7010 device will require. Therefore, a system that provides a minimum pulse width of 75ns will satisfy this maximum
requirement.
4
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