HIP7010P Просмотр технического описания (PDF) - Intersil
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HIP7010P Datasheet PDF : 20 Pages
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HIP7010
J1850 VPW Messaging
This section provides an introduction to J1850 multiplexed
communications. It is assumed that the user is or will
become familiar with the appropriate documents published
by the Society of Automotive Engineering (SAE). The follow-
ing discussion is not comprehensive.
Overview
The SAE J1850 Standard (Note 1) (J1850) establishes the
requirements for communications on a Class B multiplexed
wiring network for automotive applications. The J1850 docu-
ment details the requirements in a three layer description
which separately specifies the characteristics of the physical
layer, the data link layer, and the application layer. There are
several options within each layer which allows vehicle manu-
facturers to customize the network while still maintaining a
level of universality.
NOTE:
1. SAE J1850 Standard, Class B Data Communication Network
Interface, May 1994, Society of Automotive Engineers Inc.
The hardware of the Intersil HIP7010 provides features
which facilitate implementation of the 10.4Kbps Variable
Pulse Width Modulated (VPW) physical layer option of
J1850. In combination with a bus transceiver, such as the
Intersil J1850 Bus Transceiver HIP7020, and appropriate
software algorithms, the HIP7010 circuitry enables the
designer to completely implement a 10.4Kbps VPW Class B
Communications Network Interface per J1850. Features of
such an implementation include:
• Single Wire 10.4Kbps Communications
• Bit-by-Bit Bus Arbitration
• Industry Standard Protocol
• Message Acknowledgment (“In-Frame Response”) Capa-
bilities
• Exceptionally Tolerant of Clock Skew, System Noise, and
Ground Offsets
• Meets CARB and EPA Diagnostic Requirements
• Supports up to 32 Nodes
• Low Error Rates
• Excellent EMC Levels (when interfaced via Intersil J1850
Bus Transceiver HIP7020)
In addition to the standard J1850 features, the HIP7010 hard-
ware provides a high speed mode, (intended for receive only
use) which can significantly enhance vehicle maintenance
capabilities. The high speed mode provides a 41.6Kbps com-
munications path to any node built with the HIP7010.
Anatomy of a J1850 VPW Message
All messages in a J1850 VPW system are sent along a single
wire, shared bus. At any given moment the bus can be in
either of two states: active (high) or passive (low). Multiple
nodes are connected to the bus as a “wired-OR” network in
which the bus is high if any one (or more) node is generating
an active output. The bus is only low when no nodes are gen-
erating active outputs. It follows that, when no communica-
tions are taking place the bus will rest in the passive state. A
message begins when the bus is first driven to the high state.
Each succeeding state transition (i.e., a change from active to
passive or passive to active) transfers one bit of information
(symbol) until the message is complete and the bus once
again rests at the passive state. The interpretation of each
symbol in the message is dependent on its duration (and
state), hence, the descriptor Variable Pulse Width (VPW).
Each message has a beginning and an end, the span of
which encompasses the entire message or frame (refer to
Figure 3). A frame consists of an active start of frame (SOF)
symbol and a passive end of frame (EOF) symbol sandwiched
around a series of byte sized (8-bit) groups of symbols. The
first byte of the frame contents is always a header byte, fol-
lowed by possibly additional header bytes, followed by one or
more data bytes, followed by an integrity check byte (CRC
byte), followed by a passive end of data (EOD) symbol, fol-
lowed by possibly one or more in-frame-response (IFR) bytes.
To keep waiting times low, messages are limited to 12 bytes
total (including header, data, check, and IFR bytes). All mes-
sage bytes are transmitted most significant bit (MSB) first.
VPW Symbol Definitions
Within the J1850 scheme, symbols are defined in terms of both
duration and state (passive or active). The duration is mea-
sured as the time between successive transitions. There is one
transition per symbol and one symbol per transition. The end of
one symbol marks the beginning of the next. Since the bus is
passive when a message begins and must return to that same
state when the message completes, all frames have an even
number of transitions and hence an even number of symbols.
There are unique definitions for data bit symbols (all the sym-
bols which occur within the header, data, and check bytes) and
protocol symbols (including SOF, EOD, and EOF). The duration
of each symbol is expressed in terms of VPW Timing Pulses
(TV values). Table 1 summarizes the TV definitions. Each TV is
specified in terms of a nominal (or ideal) duration and a mini-
mum and maximum duration. The span between the minimum
and maximum limits accommodates system noise sources
such as node to node clock skew, ground offsets, clock jitter,
and electromechanical noise. There are no dead zones
between the maximum of one TV and the minimum of the next.
SOF
HEADER
DATA 1
DATA 2
CRC
FIGURE 3. TYPICAL J1850 VPW MESSAGE FRAME
EOD
EOF
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