ADSP-21160NKB-95 Просмотр технического описания (PDF) - Analog Devices

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ADSP-21160NKB-95

DSP Microcomputer

Analog Devices 

PRELIMINARY TECHNICAL DATA

April 2002

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

Reset

Table 6. Reset

Parameter

Min

Max

Unit

Timing Requirements:

tWRST

RESET Pulsewidth Low1

4tCK

ns

tSRST

RESET Setup Before CLKIN High2

8

ns

1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is

low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

2Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself

after reset.

CLKIN

RESET

tW RST

Figure 13. Reset

tSRST

REV. PrB This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

20

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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