ADSP-21160NKB-95 Просмотр технического описания (PDF) - Analog Devices

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ADSP-21160NKB-95

DSP Microcomputer

Analog Devices 

PRELIMINARY TECHNICAL DATA

April 2002

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

Power-up Sequencing

During the power up sequence of the DSP, differences in

the ramp up rates and activation time between the two power

supplies can cause current to flow in the I/O ESD protection

circuitry. To prevent this damage to the ESD diode protec-

tion circuitry, Analog Devices, Inc. recommends including

a bootstrap Schottky diode (see Figure 11 on page 18. The

bootstrap Schottky diode connected between the 1.9V and

3.3V power supplies protects the ADSP-21160N from

partially powering the 3.3V supply. Including a Schottky

diode will shorten the delay between the supply ramps and

thus prevent damage to the ESD diode protection circuitry.

With this technique, if the 1.9V rail rises ahead of the 3.3V

rail, the Schottky diode pulls the 3.3V rail along with the

1.9V rail.

Table 4. Power-up Sequencing

Parameter

Min

Max

Unit

Timing Requirements:

tRSTVDD

RESET low before V /V DDINT DDEXT on

tIVDDEVDD

tCLKVDD

tCLKRST

tPLLRST

VDDINT on before VDDEXT

CLKIN

running

after

valid

V /V 1

DDINT DDEXT

CLKIN valid before RESET de-asserted

PLL control setup before RESET de-asserted

Switching Characteristics:

tCORERST

DSP core reset de-asserted after RESET de-asserted

0

-50

0

103

TBD4

ns

200

ms

2002

ms

µs

ms

4096*tCK4,5

ms

1Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.9 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds

of milliseconds, depending on the design of the power supply subsystem.

2CLKIN should be driven coincident with power-up to avoid an undefined state in internal gates, which may cause excess current flow.

3Assumes a stable CLKIN signal after meeting worst case start up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start up time.

4Based on CLKIN cycles.

5CORERST is an internal signal only. The 4096 cycle count is dependent on tSRST specification. If setup time is not met, one additional CLKIN cycle may

be added to the core reset time, resulting in 4097 cycles maximum.

RESET

VDDINT

VDDEXT

CLKIN

tRSTVDD

tIVDDEVD D

tCLKVDD

tCLKRST

CLK_CFG3-0

CORERST

tPLLRST

tCORERST

Figure 10. Power-up Sequencing

REV. PrB This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

17

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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