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ADSP-21160NKB-95

DSP Microcomputer

Analog Devices 

PRELIMINARY TECHNICAL DATA

April 2002

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

Timing Specifications

The ADSP-21160N’s internal clock switches at higher fre-

quencies than the system input clock (CLKIN). To generate

the internal clock, the DSP uses an internal phase-locked

loop (PLL). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the DSP’s

internal clock (the clock source for the external port logic

and I/O pads).

The ADSP-21160N’s internal clock (a multiple of CLKIN)

provides the clock signal for timing internal memory,

processor core, link ports, serial ports, and external port (as

required for read/write strobes in asynchronous access

mode). During reset, program the ratio between the DSP’s

internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG3–0 pins. Even though the

internal clock is the clock source for the external port, the

external port clock always switches at the CLKIN fre-

quency. To determine switching frequencies for the serial

and link ports, divide down the internal clock, using the

programmable divider control of each port (TDIVx/RDIVx

for the serial ports and LxCLKD1–0 for the link ports).

Note the following definitions of various clock periods that

are a function of CLKIN and the appropriate ratio control:

• tCCLK = (tCK) / CR

• tLCLK = (tCCLK) ؋ LR

• tSCLK = (tCCLK) ؋ SR

Where:

• LCLK = Link Port Clock

• SCLK = Serial Port Clock

• tCK = CLKIN Clock Period

• tCCLK = (Processor) Core Clock Period

• tLCLK = Link Port Clock Period

• tSCLK = Serial Port Clock Period

• CR = Core/CLKIN Ratio (2, 3, or 4:1,

determined by CLK_CFG3–0 at reset)

• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,

determined by LxCLKD)

• SR = Serial Port/Core Clock Ratio (wide range,

determined by ؋CLKDIV)

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of

others. While addition or subtraction would yield meaning-

ful results for an individual device, the values given in this

data sheet reflect statistical variations and worst cases. Con-

sequently, it is not meaningful to add parameters to derive

longer times.

See Figure 34 under Test Conditions for voltage reference

levels.

Switching Characteristics specify how the processor

changes its signals. Circuitry external to the processor must

be designed for compatibility with these signal characteris-

tics. Switching characteristics describe what the processor

will do in a given circumstance. Use switching characteris-

tics to ensure that any timing requirement of a device

connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled

by circuitry external to the processor, such as the data input

for a read operation. Timing requirements guarantee that

the processor operates correctly with other devices.

During processor reset (RESET pin low) or software reset

(SRST bit in SYSCON register = 1), de-assertion (MS3-0,

HBG, DMAGx, RDx, WRx, CIF, PAGE, BRST) and

three-state (FLAG3-0, LxCLK, LxACK, LxDAT7-0,

ACK, REDY, PA, TFSx, RFSx, TCLKx, RCLKx, DTx,

BMS, TDO, EMU, DATA) timings differ. These occur

asynchronously to CLKIN, and may not meet the specifi-

cations published in the Timing Requirements and

Switching Characteristics tables. The maximum delay for

de-assertion and three-state is one tCK from RESET pin

assertion low or setting the SRST bit in SYSCON. During

reset the DSP will not respond to SBTS, HBR and MMS

accesses. HBR asserted before reset will be recognized, but

a HBG will not be returned by the DSP until after reset is

de-asserted and the DSP has completed bus

synchronization.

REV. PrB This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

16

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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