WM8751L Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8751L Datasheet PDF : 45 Pages
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Production Data
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
WM8751L
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
SYMBOL
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
MIN
21
21
54
60:40
TYP
MAX
UNIT
ns
ns
ns
40:60
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
SYMBOL
TMCLKL
TMCLKH
TMCLKY
MIN
TYP
MAX
UNIT
10
ns
10
ns
27
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
DACLRC
(Output)
DACDAT
tDST
tDL
tDHT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Bit Clock Timing Information
BCLK rise time (10pF load)
BCLK fall time (10pF load)
BCLK duty cycle (normal mode, BCLK =
MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
SYMBOL
tBCLKR
tBCLKF
tBCLKDS
tBCLKDS
MIN
TYP
MAX
3
3
50:50
TMCLKDS
UNIT
ns
ns
w
PD Rev 4.2 August 2006
11
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