WM8751L Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8751L

Stereo DAC For Portable Audio Applications

Wolfson Microelectronics plc 

Production Data

AUDIO INTERFACE TIMING – SLAVE MODE

BCLK

tBCH

tBCY

tBCL

DACLRC

DACDAT

tDS

tLRH

tLRSU

WM8751L

Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)

Test Conditions

DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

System Clock Timing Information

BCLK cycle time

BCLK pulse width high

BCLK pulse width low

DACLRC setup time to BCLK rising edge

DACLRC hold time from BCLK rising

edge

DACDAT hold time from BCLK rising

edge

SYMBOL

tBCY

tBCH

tBCL

tLRSU

tLRH

tDH

MIN

TYP

MAX

UNIT

50

ns

20

ns

20

ns

10

ns

10

ns

10

ns

CONTROL INTERFACE TIMING – 3-WIRE MODE

CSB

tCSL

tCSH

SCLK

tSCY

tSCH

tSCL

tSCS

tCSS

SDIN

tDSU

tDHO

LSB

Figure 4 Control Interface Timing – 3-Wire Serial Control Mode

w

PD Rev 4.2 August 2006

13

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