WM8751L Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8751L Datasheet PDF : 45 Pages
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WM8751L
Production Data
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
500
SCLK pulse cycle time
tSCY
200
SCLK pulse width low
tSCL
80
SCLK pulse width high
tSCH
80
SDIN to SCLK set-up time
tDSU
40
SCLK to SDIN hold time
tDHO
40
CSB pulse width low
tCSL
40
CSB pulse width high
tCSH
40
CSB rising to SCLK rising
tCSS
40
Pulse width of spikes that will be suppressed
tps
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t5
t3
SDIN
t4
t6
t2
t8
SCLK
t1
t7
t9
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
MIN
TYP
MAX
UNIT
0
526
kHz
1.3
ns
600
us
600
ns
600
ns
100
ns
300
ns
300
ns
600
ns
900
ns
0
5
ns
w
PD Rev 4.2 August 2006
14
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