TMC2072KHC Просмотр технического описания (PDF) - Fairchild Semiconductor

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производитель

TMC2072KHC

Genlocking Video Digitizer

Fairchild Semiconductor 

PRODUCT SPECIFICATION

Details (continued)

Bit

Name

0

ENAGC

Reg 0D Sync Tip Set

7:4

3:0

ST[3:0]

Reg 0E

7

FLIPPX

6

FLIPLDV

5

XDLY

4

VDLY

3

ENVHCVBS

2

FORCEZERO

1:0

Reg 0F

7:0

TMC2072

Function

Re-Enable Automatic Gain Control. HIGH (self-resetting one-shot): Initiates a

new, self-terminating one-frame AGC sequence, independent of sync lock status.

LOW (power-on default and self-reset): AGC is enabled for one frame when video

sync is initially acquired, and each time sync is lost and reacquired. [TMC22071A

bit 25].

Reserved

Programmable Sync Tip Value. Power-on default = 0. Recommended setting =

3. When the chip has achieved stable lock, this will be the average value output

over CVBS during sync tips and equalization pulses. [TMC22071A bit 43:40.]

LOW (power-on default): Phase of PXCK output matches that of the TMC22071A.

HIGH: Phase of PXCK output is inverted, relative to that of the TMC22071A.

LOW (power-on default): Phase of LDV output matches that of the TMC22071A.

HIGH: Phase of LDV output is inverted, relative to that of the TMC22071A.

LOW (power-on default): PXCK output timing matches that of TMC22071A.

HIGH: PXCK output is delayed approximately 5-10ns, to simplify interface timing

in some systems.

LOW (power-on default): LDV output timing matches that of TMC22071A. HIGH:

LDV output is delayed approximately 5-10ns, to simplify interface timing in some

systems.

LOW (power-on default): Digital outputs CVBS0-7, FID(2:0) and GV/GHSYNC

are tristated, to avoid bus contentions elsewhere on the system. HIGH: These

pins are enabled, for normal operation.

LOW (power-on default): If the Hloop loses lock (Hlock\ goes high), the CVBS

port will output the default subcarrier frequency and cumulative phase keyed to

each GHSYNC falling edge, and the raw output of the A/D converter at all other

times. In this case, since the incoming video and internal state machine are

asynchronous, GRS data may appear anywhere along each digitized video line.

HIGH: If the Hloop loses lock, the CVBS data port will yield only the default

subcarrier phase and frequency data, and zero at all other times.

Reserved, reset low (power-on default)

Reserved, reset low (power-on default)

REV. 1.0.4 6/19/01

11

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