TMC2072KHC Просмотр технического описания (PDF) - Fairchild Semiconductor
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TMC2072KHC Datasheet PDF : 21 Pages
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PRODUCT SPECIFICATION
TMC2072
Switching Characteristics (for standard temperature range)
Parameter
tDO
Output Delay Time
tHO
Output Hold Time
fPCK
Pixel Rate
fPXCK Master Clock Rate
tPWHPX
tPWHPX
tDH
PXCK Pulse Width, LOW
PXCK Pulse Width, HIGH
Horizontal Sync to GHSYNC
tVD
Vertical Sync to GVSYNC
tXL
PXCK LOW to LDV HIGH
tXV
PXCK LOW to LDV LOW
Conditlons
CLOAD = 35 pF
TMC2072
TMC2072-1
27 MHz
27 MHz
For low-jitter video source,
Lead - Lag = 80h
For low-jitter video source,
Lead - Lag = 80h
FLIPPX = 0, FLIPLDV = 0
XDLY = 0, VDLY = 0
Min.
2
3
12
24
12
12
Typ.
14
Max.
15
8
15.3
27.4
30.6
Unit
ns
ns
MHz
MHz
ns
ns
pxck
14
pxck
10
ns
6
ns
System Performance Characterlstics
Parameter
ESCH
ESCP
tAL
VXT
Sync time-base variation1
Subcarrier Phase Error1
Line-lock Acquisition Time
Channel-to-Channel Crosstalk @3.58 Mhz
Min.
Typ.
Note:
1. NTSC/PAL compliant black burst at nominal input level ±10%, frequencies nominal ±10 ppm.
Max.
±3
±2
2
-35
Unit
ns
degrees
frames
dB
Video A
LPF
Video B
LPF
Video C
LPF
20 MHz, TTL
+5V
Digital Supply Plane
10µF
Ferrite Bead
Analog Supply Plane*
10µF
6.8 pF
10µH
150 pF
390
pF 0.01 µF
3.3 µF
75Ω 3.3 µF
75Ω 3.3 µF
75Ω
+5V
0.1µF
0.1µF
DGND VDD VDDA AGND
VIN1
DDS OUT
PFD IN
COMP
VREF
+5V
0.1µF
3.3KΩ
VIN2
VIN3
EXT PXCK
CLK IN
CLK OUT
PXCK SEL
TMC2072
Genlocking
Video Digitizer
CBYP
0.1µF
LM385-1.2
RT
RB
CVBS7:0
GHSYNC
GVSYNC
PXCK
LDV
0.1µF
0.1µF
8
0.1µF
and must be connected
via low-impedance path
MICROPROCESSOR
INTERFACE
Figure 16. Typical Interface Circuit
65-2072-16
*section of supply plane beneath
analog interface circuitry
REV. 1.0.4 6/19/01
17
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