SAA7390 Просмотр технического описания (PDF) - Philips Electronics

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SAA7390

High performance Compact Disc-Recordable (CD-R) controller

Philips Electronics 

Philips Semiconductors

High performance Compact

Disc-Recordable (CD-R) controller

Preliminary specification

SAA7390

7 FUNCTIONAL DESCRIPTION

7.1 Input clock doubler

To facilitate compatibility of the SAA7390 with all of the

available CD decoders, a clock doubler has been included.

This clock doubler may take a 16.9344 MHz clock and

double this when requested to do so by the

microcontroller. Logic has been included to remove the

possibility of a ‘runt’ clock pulse when the doubler is

engaged. Once engaged, the only way to disengage it is

via a reset condition.

7.2 Block encoder

To support the write function, a modified version of the

CDB2 function has been included. The block encoder

accepts parallel data from the buffer manager, serializes it,

calculates the CRC and third-level ECC parity bytes and

appends them when and where necessary. The RAM

required during the parity calculation is included on the

SAA7390.

The following modifications to the CDB2 have been made:

• Word select in bypass mode has been inverted to match

the data mode

• The ‘end-of-frame’ signal is now generated during the

bypass and CD-ROM mode and will interrupt the

microcontroller at the end of each frame

• The ‘end-of-frame’ signal is also used to correctly

synchronize between bypass mode and regular data

mode at the end of a frame. The modes programmed

into the CDB2 command, header, sub-header and block

size registers will automatically switch in or out at the

end of frame

• DRQ in CCMD is also synchronized to frame boundaries

using the ‘end-of-frame’ signal. This change is valid for

both bypass and regular data modes.

7.3 Front-end

The front-end section of the SAA7390 is identical to the

front-end of the mini-SEQUOIA (also found on the

SAA7385), with the exception of the Serial Peripheral

Interface (SPI). The front-end is comprised of many

sub-sections.

7.3.1 BLOCK DECODER

The block decoder first reverses the bits of each received

byte and then runs them through a linear feedback shift

register to be de-scrambled. The polynomial used to

de-scramble the serial data is as follows: X15 + X + 1

It also detects and tests the synchronization field and will

start the data clock when commanded. The de-scrambled

header is assembled into four registers with header ready

and header error status (see HDRRDY and HDRERR in

RDDSTAT). The data clock does not have to be enabled

to receive valid headers.

Also included in this section is the logic required to decide

when to automatically start collecting data and sub-code

information based on the contents of the Q-channel

registers.

7.3.2 SECTOR SEQUENCER

The sector sequencer de-serializes the data and error

flags from the block decoder and determines when to:

• Write data to the buffer

• Write flags to the buffer

• Test the header to determine the Mode

• Test the sub-header to determine the Form

• Test the CRC

• End the sector and write the status byte to the buffer.

Included in the sector sequencer is the CRC generator

which checks each Yellow book or Green book sector as it

is shifted into the SAA7390 in accordance with the

following polynomial:

X32 + X31 + X16 + X15 + X4 + X3 + X + 1

The status of each sector is saved and written to the buffer

at the end of the sector.

7.3.3 SUB-CODE RECEIVE AND Q-CHANNEL EXTRACTOR

A UART which samples asynchronous bits on a 24 clocks

per bit basis is included. This is required because the

CD-60 based decoders output the sub-code data at

nominally 24 clocks per bit, but not synchronized to the

data. Also included is a sub-code synchronization detector

which senses the beginning of each new sector of

sub-code information. The serial sub-code information is

assembled into bytes in the following order:

Data bits 7 to 0 = 0, Q, R, S, T, U, V and W.

As each byte is assembled, it is sent to the buffer manager

to be written to the DRAM buffer. At the same time, the

Q-channel bits are assembled into bytes and sent to the

buffer. All Q-channel bytes except CRC are sorted in

registers for use by the microcontroller. The Q-channel

CRC (last two bytes) is checked just before the end of the

sub-code sector. If the CRC check fails, BADQ in

RDDSTAT is available to the microcontroller and is written

into the buffer at the end of the sector.

1996 Jul 02

11

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