SAA7390 Просмотр технического описания (PDF) - Philips Electronics

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SAA7390

High performance Compact Disc-Recordable (CD-R) controller

Philips Electronics 

Philips Semiconductors

High performance Compact

Disc-Recordable (CD-R) controller

Preliminary specification

SAA7390

When the ten Q-channel registers have been updated,

QFRMRDY in RDDSTAT is set. The ten Q-channel

registers are valid while QFRMRDY is set. In the audio

mode, HDRRDY in RDDSTAT generates this interrupt, but

the QFRMRDY bit will still be available as status to the

microcontroller.

7.3.4 C-FLAG RECEIVER

The C-flag bits, or corrector flags, are also 24 data clocks

long and reception of these bits is achieved using the

same method as for the sub-code; in this event, the C-flag

data is synchronized to the data.

The difference is that only one bit is used; F1, the absolute

time synchronization information. When in audio mode

and ENABRED in FECTL is set, receipt of F1 set will start

the internal data clock after the next rising edge of word

strobe (WSAB) which is the left channel sample when the

CD-60 decoder is programmed for EIAJ audio format.

When in audio mode, the Q-channel information provides

the MSF address and the F1 flag provides the start of

frame information; together these provide an absolute byte

address on the disc.

7.3.5 S2B UART

This UART is provided for communication with a second

slave microcontroller. It is hard-wired for one start-bit, eight

data bits, a parity bit and one stop bit. Parity testing can be

programmed to be either odd parity or even parity. Parity

error and over-run status are provided via PE and

OVRRUN in S2BSTAT. Selectable baud rates of

31.25, 62.5 and 187.5 kbaud are available via S2BSEL1

and S2BSEL0 in BRGSEL. Once the start-bit is found, the

data sampling time does not adapt dynamically, therefore

parity errors may occur depending on the baud rate

selected.

7.3.6 SPI UART

This UART is provided for communication with a second

slave microcontroller used in Philips CD-R engines.

7.3.7 WATCH-DOG TIMER

A pair of counters are included which output a 967 µs reset

pulse to the entire chip and the SYSRES and SYSRES

pins if the timer is not reset during the 212 ms time-out

period. The watch-dog timer is reset by setting RWMD in

FECTL HIGH then LOW. If RWMD is left HIGH, the

watch-dog function is disabled.

7.3.8 GLUE LOGIC (GLIC)

The final block of logic in the front-end consists of:

a programmable, linear pulse-width modulator for

spindle-motor control; an address de-multiplexer for the

address/data bus of the microcontroller; plus audio

multiplexing and muting circuitry for full control of Red

book audio data to an external Digital-to-Analog Converter

(DAC).

7.4 Track descriptor block

Logic has been included to simplify the creation of the

track descriptor block. This is achieved by allowing one

frame to be repeated a selectable number of times. Once

this repeated pattern is complete, the normal data is then

sent to the front-end.

1996 Jul 02

12

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