SAA7390 Просмотр технического описания (PDF) - Philips Electronics

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SAA7390

High performance Compact Disc-Recordable (CD-R) controller

Philips Electronics 

Philips Semiconductors

High performance Compact

Disc-Recordable (CD-R) controller

Preliminary specification

SAA7390

8.3 Microprocessor interrupts

An interrupts pulse is generated upon completion of any of the following commands:

• CALCULATE_SYNDROMES (not Mode 2, Form 1)

• CALCULATE_SYNDROMES (Mode 2, Form 1)

• CRC_RECALCULATE (not Mode 2, Form 1)

• CRC_RECALCULATE (Mode 2, Form 1)

• COPY_RESULTS (not Mode 2, Form 1)

• COPY_RESULTS (Mode 2, Form 1)

• CORRECT_P_SYNDROMES

• CORRECT_Q_SYNDROMES

• TEST_ECC_ROM

• TEST_ECC_RAM_READ

• TEST_ECC_RAM_WRITE.

If a command is aborted by the ASSERT_ABORT command, a spurious interrupt may be generated within five clock

cycles of the ASSERT_ABORT command.

Table 7 Command execution times; note 1

COMMAND

CALCULATE_SYNDROMES (not Mode 2, Form 1)

CALCULATE_SYNDROMES (Mode 2, Form 1)

CRC_RECALCULATE (not Mode 2, Form 1)

CRC_RECALCULATE (Mode 2, Form 1)

COPY_RESULTS (not Mode 2, Form 1)

COPY_RESULTS (Mode 2, Form 1)

CORRECT_P_SYNDROMES

(maximum addition per correction)

CORRECT_Q_SYNDROMES

(maximum addition per correction)

TEST_ECC_RAM_READ

TEST_ECC_RAM_WRITE

CYCLES

5 604

5 600

4 136

4 120

1 148

1 156

1 466

157

888

167

1 184

1 184

TIME (µs)

at 33 MHz

186.8

186.7

137.9

137.3

38.3

38.5

48.9

5.2

29.6

5.6

39.5

39.5

MEMORY

ACCESSES

2 658

2 654

2 068

2 060

574

578

0

2

0

2

592

592

Note

1. All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections.

P and Q corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh

timing, other buffer traffic, and configuration of nibble-wide memory.

8.3.1 INTERRUPT REGISTER DEFINITIONS

Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be

enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output

latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt,

the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the

interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any

1996 Jul 02

20

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