MT90881 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT90881 Datasheet PDF : 97 Pages
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MT90880/1/2/3
Data Sheet
Signal
iddq
sclk_AT1
I/O
I AD23
O B26
pclk_AT1
O AF24
ram_clk
O Y2
Width
Description
Table 12 - Test Facilities
IDDQ test enable.
Set low for normal operation.
Analog test output for system clock
PLL. Leave unconnected in normal
operation.
Analog test output for PCI clock PLL.
Leave unconnected in normal
operation.
66 MHz memory clock output.
This is used for test purposes only.
Leave unconnected in normal
operation.
3.7.3 Test Operating Modes
1) Normal operating mode (T_MODE[1:0] = '11')
The device samples the T_D pins to determine the required operating mode shortly after reset is released.
These pins are known as the "bootstrap controls". The device has internal pull-up (100 KΩ ±30%) resistors
connected to the T_D bus pins. To pull-low connect a 10 KΩ pull-down resistor to ground. Bootstrap controls
are as follows:
T_D
15
14
13:11
10:8
7
6
5
4
3
2
0:1
Function
Notes
Reserved
Reserved
Reserved
Selects delay of RAM_CLK output relative to
S_CLK.
Pull low to bypass PCI_CLK PLL.
Pull low to bypass the S_CLK PLL.
Controls m_mint0 and m_mint1 polarity - pull low
for active low and leave unconnected for active
high.
Pull low to enable RAM_CLK output (otherwise it
will be high impedance).
Pull low for freeze enable.
Pull low for simulation speed-up.
This reduces the number of cycles that the chip is
held in reset after S_RST# and PCI_RST# have
gone high from 16348 to 256.
This should not be used during normal operation,
since the PLLs will not have time to lock.
Reserved
Pull low for normal operation.
Leave unconnected in normal operation.
Leave unconnected in normal operation.
Leave unconnected in normal operation.
See Table 21.
Leave unconnected in normal operation.
Leave unconnected in normal operation.
Leave unconnected in normal operation.
Table 13 - Bootstrap Pin Functions
19
Zarlink Semiconductor Inc.
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