MT90881 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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производитель

MT90881

TDM to Packet Processors

Zarlink Semiconductor Inc 

MT90880/1/2/3

Data Sheet

Signal

ref_clk

RMII Port A

rm0_rxd[1:0]

rm0_rxdv/ crs

rm0_txen

rm0_txd[1:0]

RMII Port B

rm1_rxd[1:0]

rm1_rxdv/ crs

rm1_txen

rm1_txd[1:0]

I/O

I U AB11

Package Balls

Description

Synchronous clock reference for receive,

transmit and control interface.

Common to both RMII ports.

I U AE9 [1], AD9 [0]

I D AF7

O U AD6

O U AE6 [1], AD7 [0]

Receive data

Carrier sense & receive data valid

Transmit enable

Transmit data

I U AE13 [1], AF13 [0]

Receive data

I D AE12

Carrier sense & receive data valid

O U AD10

Transmit enable

O U AF10 [1], AD11 [0]

Transmit data

Table 7 - RMII Interface

3.4 PCI Interface

The PCI signals are NOT 5 V tolerant.

All PCI outputs are high impedance while S_RST is low.

Active low signals are designated by a # suffix, in accordance with the convention used in the PCI specification.

Signal

pci_clk

pci_rst#

pci_req#

pci_gnt#

pci_ad[31:0]

pci_cbe[3:0]#

pci_par

pci_frame#

I/O

Package Balls

Description

I AF20

PCI clock

I AE19

PCI reset

O AC19

PCI request

I AD19

PCI grant

I O AE20 [31], AB19 [30], AF21 [29], AC20 [28], PCI address / data

AD20 [27], AE21 [26], AF22 [25], AD21 [24],

AF23 [23], AD22 [22], AE23 [21], AC21 [20],

AE24 [19], AC22 [18], AD24 [17], AC23 [16],

AC26 [15], AB25 [14], W23 [13], AA24 [12],

AB26 [11], AA25 [10], Y24 [9], AA26 [8],

V24 [7], U23 [6], V25 [5], T23 [4] T24 [3],

R23 [2], T25 [1], T26 [0]

I O AE22 [3], AB23 [2], Y23 [1], W24 [0]

PCI control / byte enable

I O AC25

PCI parity

I O AE25

PCI frame

16

Zarlink Semiconductor Inc.

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