MT90881 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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производитель

MT90881

TDM to Packet Processors

Zarlink Semiconductor Inc 

MT90880/1/2/3

Data Sheet

Signal

pci_trdy#

pci_irdy#

pci_stop#

pci_devsel#

pci_idsel

pci_perr#

pci_serr#

I/O

I O AA23

I O AF26

I O AC24

I O AE26

I AB20

I O AD26

I O AB24

pci_lock#

pci_inta#

PCI_M66EN

I O Y22

I O AF19

I O Y25

Package Balls

Table 8 - PCI Interface

Description

PCI target ready

PCI initiator ready

PCI stop

PCI device select

PCI ID select

PCI parity error

PCI system error (NOT open drain.

See “Open Drain Circuitry” on

page 71)

PCI lock. Refer to PCI spec section

2.2.3

PCI interrupt (NOT open drain. See

“Open Drain Circuitry” on page 71)

33 MHz /66 MHz select

3.5 External Memory Interface

The external memory signals are NOT 5 V tolerant.

Active low signals are designated by a # suffix, in accordance with the convention used in common memory

data sheets

Signal

ram_d[31:0]

ram_a[22:2]

ram_adsc#

ram_we[3:0]#

ram_oe[3:0]#

I/O

Package Balls

IOU N2 [31], R4 [30], N1 [29], R5 [28],

P1 [27], T4 [26], P2 [25], P3 [24],

R1 [23], AB4 [22], AC2 [21], AD1 [20],

AC3 [19], AD2 [18], AC4 [17], AE1 [16],

AE2 [15], AD3 [14], AC5 [13], AF1 [12],

AF2 [11], AC6 [10], AE3 [9], AF3 [8],

AD4 [7], AB7 [6], AE4 [5], AF4 [4],

AD5 [3], AC7 [2], AE5 [1], AB8 [0]

O T5 [22], R3 [21], U4 [20],

T1 [19], U5 [18], T2 [17], T3 [16],

U1 [15], U2 [14], U3 [13], V4 [12],

V1 [11], V5 [10], V2 [9], W4 [8],

W1 [7], W2 [6], Y1 [5], W5 [4],

W3 [3], Y4 [2]

O U AB3

O U Y5 [3], AA1 [2], Y3 [1], AA2 [0]

O U AB1 [3], AA4 [2], AB2 [1], AC1 [0]

Description

Buffer memory data

Buffer memory address

(up to 8 MBytes)

Buffer memory address status control

Buffer memory write chip select

Buffer memory read chip select

Table 9 - External Memory Interface

17

Zarlink Semiconductor Inc.

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