MT90221AL Просмотр технического описания (PDF) - Mitel Networks
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MT90221AL Datasheet PDF : 114 Pages
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MT90221
VSS
REFCK_3
REFCK_2
REFCK_1
REFCK_0
SR_A_18
SR_A_17
SR_A_16
SR_A_15
SR_A_14
VDD
VSS
SR_A_13
SR_A_12
SR_A_11
SR_A_10
VDD
VSS
SR_A_9
SR_A_8
SR_A_7
SR_A_6
SR_A_5
VDD
VSS
SR_A_4
SR_A_3
SR_A_2
SR_A_1
SR_A_0
SR_WE
SR_D_7
SR_D_6
SR_D_5
SR_D_4
SR_D_3
VDD
VSS
SR_D_2
SR_D_1
SR_D_0
SR_CS 1
SR_CS_0
VSS
VDD
RXSOC
RXCLAV
VDD
RXDATA_7
RXDATA_6
RXDATA_5
VSS
156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106
104
158
102
160
100
162
98
164
96
166
94
168
92
170
90
172
88
174
86
176
84
178
82
180
80
182
208 PIN MQFP
78
184
76
186
74
188
72
190
70
192
68
194
66
196
64
198
62
200
60
202
58
204
56
206
54
208
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
VSS
TXCKIO_2
VDD
TXCKIO_3
VSS
DSTO_3
TXSYNCIO_3
NC
NC
VSS
NC
VDD
NC
VSS
NC
NC
NC
NC
VDD
NC
VSS
NC
VDD
NC
NC
VSS
VDD
TEST2
TEST1
VDD
CLK
VSS
TCK
TMS
TDI
TRST
TDO
UP_IRQ
VDD
UP_A_0
UP_A_1
UP_A_2
UP_A_3
UP_A_4
UP_A_5
UP_A_6
UP_A_7
UP_A_8
UP_A_9
UP_A_10
RESET
VSS
Pin Description
Figure 2 - Pin Connections
Pin #
Name I/O
Description
22, 23,
24, 25, 26,
27, 28, 29
21
TxData
[7:0]
TxSOC
ATM Input Port Signals (UTOPIA Transmit Interface)
I UTOPIA Transmit Data Bus. Byte-wide data driven from ATM LAYER device to
MT90221. Bit 7 is the MSB. All arriving data between the last byte of the previous
cell and the first byte of the following cell (indicated by the SOC signal) is ignored.
I UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM
LAYER device when TxData[7:0] contains the first valid byte of the cell. After this
signal is high, the following 52 bytes should contain valid data. The MT90221 waits
for another TxSOC signal after reading a complete cell.
3
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