MT90221AL Просмотр технического описания (PDF) - Mitel Networks

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MT90221AL

Quad IMA/UNI PHY Device

Mitel Networks 

MT90221

Pin Description (continued)

Pin #

32

30

20

34, 35, 36,

37, 38

205, 206,

207, 2, 3,

4, 5, 6

202

15

17

203

9, 10, 11,

12, 13

188, 189,

190, 191,

192, 195,

196,197

Name I/O

Description

TxClk

TxEnb

TxClav

TxAddr

[4:0]

I UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the

MT90221 which synchronizes data transfers on TxData[1:0]. This signal is the

clock of the incoming data. Data is sampled on the rising edge of this signal.

I UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER

device during cycles when TxData contains valid cell data.

O UTOPIA Transmit Cell Available Indication Signal. For cell-level flow control in a

MPHY environment, TxClav is an active high tri-stateable signal from the MT90221

to the ATM LAYER device. A polled MT90221 drives TxClav only during each cycle

following one with its address on the TxAddr lines. The polled MT90221 asserts

TxClav high to indicate it can accept the transfer of a complete cell, otherwise it de-

asserts the signal.

I Transmit Address.Five bit wide true data driven from the ATM to the PHY layer to

poll and select the appropriate MT90221. TxAddr[4] is the MSB. Each MT90221

keeps its addresses. The value for the Tx and Rx portions of the MT90221 can be

different

ATM Output Port Signals (UTOPIA Receive Interface) (see Note 1)

RxData

[7:0]

RxSOC

RxClk

RxEnb

RxClav

RxAddr

[4:0]

O UTOPIA Receive Data Bus. Byte-wide data driven from MT90221 to ATM layer

device. RxData[1] is the MSB. To support multiple PHY configurations, RxData is

tri-stateable, enabled only in cycles following those with RxEnb asserted.

O UTOPIA Receive Start of Cell Signal. Active high asserted by the MT90221 when

RxData contains the first valid byte of a cell. To support multiple PHY

configurations, RxSOC is tri-stateable, enabled only in cycles following those with

RxEnb asserted.

I UTOPIA Receive Byte Clock. This signal is the clock of the outgoing data. Data

changes after the rising edge of this signal. The RxClk needs to be synchronized

with the system clock.

I UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer

device to indicate that RxData[3:0] and RxSOC will be sampled at the end of the

next cycle. In multiple PHY configurations, RxEnb* is used to tri-state RxData and

RxSOC MT90221 outputs. In that case, RxData and RxSOC would be enabled only

in cycles following those with RxEnb asserted.

O UTOPIA Receive Cell Available Indication Signal. For cell-level flow control in a

MPHY environment, RxClav is an active high tri-stateable signal from the MT90221

to ATM LAYER device. A polled MT90221 drives RxClav only during each cycle

following one with its address on the TxAddr lines. The polled MT90221 asserts

RxClav high to indicate it has a complete cell available for transfer to the ATM Layer

device, otherwise it de-asserts the signal. This signal indicates cycles when there is

valid information on RxData / RxSOC.

I Receive Address. Five bit wide true data driven from the ATM to PHY layer to

select the appropriate MT90221. RxAddr[4] is the MSB. Each MT90221 keeps its

address. The value for the Tx and Rx portions of the MT90221 can be different.

Receiver Static Memory Interface Signals (see Note 1)

sr_d I/O Static Memory Data Bus. Data Bus to exchange data between the MT90221 and

[7:0]

the external static memory.

4

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