56F8156 Просмотр технического описания (PDF) - Freescale Semiconductor

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56F8156

16-bit Digital Signal Controllers

Freescale Semiconductor 

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued)

Signal Name Pin No. Type

State

During

Reset

Signal Description

RD

45

Output

In reset, Read Enable — RD is asserted during external memory read

output is cycles. When RD is asserted low, pins D0 - D15 become inputs

disabled, and an external device is enabled onto the data bus. When RD is

pull-up is deasserted high, the external data is latched inside the device.

enabled When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn

pins. RD can be connected directly to the OE pin of a Static RAM

or ROM.

Depending upon the state of the DRV bit in the EMI bus control

register (BCR), RD is tri-stated when the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead of

using the default setting.

To deactivate the internal pull-up resistor, set the CTRL bit in the

SIM_PUDR register.

WR

44

Output

In reset, Write Enable — WR is asserted during external memory write

output is cycles. When WR is asserted low, pins D0 - D15 become outputs

disabled, and the device puts data on the bus. When WR is deasserted high,

pull-up is the external data is latched inside the external device. When WR is

enabled asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can

be connected directly to the WE pin of a static RAM.

Depending upon the state of the DRV bit in the EMI bus control

register (BCR), WR is tri-stated when the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead of

using the default setting.

PS

(CS0)

To deactivate the internal pull-up resistor, set the CTRL bit in the

SIM_PUDR register.

46

Output

In reset, Program Memory Select — This signal is actually CS0 in the

output is EMI, which is programmed at reset for compatibility with the

disabled, 56F80x PS signal. PS is asserted low for external program

pull-up is memory access.

enabled

Depending upon the state of the DRV bit in the EMI bus control

register (BCR), CS0 is tri-stated when the external bus is inactive.

CS0 resets to provide the PS function as defined on the 56F80x

devices.

(GPIOD8)

Input/

Output

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

To deactivate the internal pull-up resistor, clear bit 8 in the

GPIOD_PUR register.

56F8356 Technical Data, Rev. 13

24

Freescale Semiconductor

Preliminary

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