56F8156 Просмотр технического описания (PDF) - Freescale Semiconductor

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56F8156

16-bit Digital Signal Controllers

Freescale Semiconductor 

Signal Pins

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued)

Signal Name Pin No. Type

State

During

Reset

Signal Description

A8

19

Output

In reset, Address Bus— A8 - A15 specify eight of the address lines for

output is external program or data memory accesses.

disabled,

pull-up is Depending upon the state of the DRV bit in the EMI bus control

enabled register (BCR), A8 - A15 and EMI control signals are tri-stated when

the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead of

using the default setting.

(GPIOA0)

A9

(GPIOA1)

A10

(GPIOA2)

A11

(GPIOA3)

A12

(GPIOA4)

A13

(GPIOA5)

A14

(GPIOA6)

A15

(GPIOA7)

Schmitt

Input/

20

Output

21

22

23

24

25

26

Port A GPIO — These eight GPIO pins can be individually

programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOA_PUR register.

Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.

56F8356 Technical Data, Rev. 13

Freescale Semiconductor

21

Preliminary

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