MAX3672 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3672

Low-Jitter 155MHz/622MHz Clock Generator

Maxim Integrated 

Low-Jitter 155MHz/622MHz Clock Generator

Functional Diagram

C1

R1

R3

VCO

KVCO

C3

C1

R1

LOL THADJ CTH

VC COMP POLAR OPAMP-

OPAMP+

LOL

OPAMP

REFCLK+

PECL

REFCLK-

RSEL

VSEL

VCOIN+

VCOIN-

PECL

DIV (N3)

1/2/8

DIV (N1)

4/8/32

MAX3672

DIVIDER

CONTROL LOGIC

DIV

(N2)

PFD/CP

Kpd

DIV

(N2)

PECL

DIV

1/2/4/8

PECL

GSEL

C2-

C2+

MOUT+

MOUT-

POUT+

POUT-

NSEL1

NSEL2

PSEL1

PSEL2

VFILTER

Detailed Description

The MAX3672 contains all the blocks needed to form a

PLL except for the VCO, which must be supplied sepa-

rately. The MAX3672 consists of input buffers for the ref-

erence clock and VCO, input and output clock-divider

circuitry, LOL detection circuitry phase detector, gain-

control logic, a phase-frequency detector and charge

pump, an op amp, and PECL output buffers.

This device is designed to clean up the noise on the ref-

erence clock input and provide a low-jitter system clock

output. This device also supports frequency conversion.

Input Buffer for Reference

Clock and VCO

The MAX3672 contains differential inputs for the refer-

ence clock and the VCO. These high impedance inputs

can be DC-coupled and are internally biased with so

that they can be AC-coupled (Figure 1 in the Interface

Schematic section). A single-ended VCO or reference

clock can also be applied.

Input and Output Clock-Divider Circuitry

The pre-dividers scale the input frequencies of the VCO

and reference clock. Clock-divider ratios N1 and N3

must be chosen so that the output frequencies of the

pre-dividers are equal. The maximum allowable pre-

divider output frequency is 77.76MHz (Table 1).

The main dividers (N2) facilitate tuning the loop band-

width by setting the frequency divider ratio. The divider

control logic can be programmed to divide from 1 to 256

in binary multiples (Table 3). The POUT output buffer is

preceded by a clock divider that scales the main clock

output by 1, 2, 4, or 8 to provide an optional clock.

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