MAX3672 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3672

Low-Jitter 155MHz/622MHz Clock Generator

Maxim Integrated 

Low-Jitter 155MHz/622MHz Clock Generator

Table 2. RSEL and VSEL Settings

INPUT PIN

VSEL

VCO DIVIDER INPUT PIN

N1

RSEL

REFERENCE-

CLOCK

DIVIDER N3

VCC

4

VCC

1

OPEN

8

OPEN

2

GND

32

GND

8

Table 3. Divider Logic Setup

INPUT PIN NSEL1 INPUT PIN NSEL2

VCC

VCC

OPEN

VCC

GND

VCC

VCC

OPEN

OPEN

OPEN

GND

OPEN

VCC

GND

OPEN

GND

GND

GND

DIVIDER RATIO N2

1

2

4

8

16

32

64

128

256

Table 4. Phase Detector Gain Setup

INPUT PIN GSEL

OPEN or VCC

GND

Kpd (µA/UI)

20

5

Table 5. Optional Clock Setup

INPUT PIN

PSEL1

VCC

GND

VCC

GND

INPUT PIN

PSEL2

VCC

VCC

GND

GND

VCO TO POUT

DIVIDER RATIO

1

2

4

8

Setting the Higher-Order Poles

Spurious noise is generated by the phase detector

switching at the compare frequency, where fCOMPARE

= fVCO/(N1 ✕ N2). Reduce the spurious noise from the

digital phase detector by placing a higher-order pole

(HOP) at a frequency much less than the compare fre-

quency. The HOP should, however, be placed high

enough in frequency that it does not decrease the over-

all loop-phase margin and impact jitter peaking. These

two conditions can be met by selecting the HOP fre-

quency to be (K ✕ 4) < fHOP < fCOMPARE, where K is

the loop bandwidth.

The HOP can be implemented either by providing a

compensation capacitor C2, which produces a pole at:

f HOP

=

1

2π(20kΩ)(C2 )

or by adding a lowpass filter, consisting of R3 and C3,

directly on the VCO tuning port, which produces a pole at:

f HOP

=

1

2πR3 C3

Using R3 and C3 might be preferable for filtering more

noise in the PLL, but it might still be necessary to provide

filtering through C2 when using large values of R1 and N1

✕ N2, to prevent clipping in the op amp.

Setting the Optional Output

The MAX3672 optional clock output can be set to binary

subdivisions of the main clock frequency. The PSEL1

and PSEL2 pins control the binary divisions. Table 5

shows the pin configuration and possible divider ratios.

Applications Information

PECL Interfacing

The MAX3672 outputs (MOUT+, MOUT-, POUT+,

POUT-) are designed to interface with PECL signal levels

and should be biased appropriately. Proper termination

requires an external circuit that provides a Thevenin

equivalent of 50Ω to VCC - 2.0V and controlled-imped-

ance transmission lines. To ensure best performance,

the differential outputs must have balanced loads. If the

optional clock output is not used, the output can be left

floating to save power.

Layout

The MAX3672 performance can be significantly affected

by circuit board layout and design. Use good high-

frequency design techniques, including minimizing

ground inductance and using fixed-impedance trans-

mission lines on the reference and VCO clock signals.

Power-supply decoupling should be placed as close to

the die as possible. Take care to isolate the input from

the output signals to reduce feedthrough.

VCO Selection

The MAX3672 is designed to accommodate a wide

range of VCO gains, positive or negative transfer

slopes, and VCC-referenced or ground-referenced con-

trol voltages. These features allow the user a wide

range of options in VCO selection; however, the proper

VCO must be selected to allow the clock generator cir-

cuitry to operate at the optimum levels. When selecting

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