LC651154F Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC651154F

Four-Bit CMOS Microcontrollers for Small-Scale Control Applications

SANYO -> Panasonic 

LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)

Parameter

High-level input current

Low-level input current

High-level output voltage

Low-level output voltage

Symbol

IIH (1)

IIH (2)

IIH (3)

IIL (1)

IIL (2)

IIL (3)

IIL (4)

VOH (1)

VOH (2)

VOL (1)

VOL (2)

Conditions

Applicable pins and notes

min

• Output n-channel transistors off

(Including the n-channel transistor

off leakage current.)

• VIN = 13.5 V

• Output n-channel transistors off

(Including the n-channel transistor

off leakage current.)

• VIN = VDD

When an external clock is used,

VIN = VDD

• Output n-channel transistors off

• VIN = VSS

• Output n-channel transistors off

• VIN = VSS

VIN = VSS

When an external clock is used,

VIN = VSS

• IOH = –50 µA

• VDD = 4.0 to 6.0 V

IOH = –10 µA

Ports C, D, E and F with

the open-drain

specifications

Ports A and G with the

open-drain specifications

OSC1

Ports with the open-drain

specifications

Ports with the pull-up

resistor specifications

RES

OSC1

Ports with the pull-up

resistor specifications

Ports with the pull-up

resistor specifications

–1.0

–1.3

–45

–1.0

VDD – 1.2

VDD – 0.5

• IOL = 10 mA

• VDD = 4.0 to 6.0 V

Port

When IOL = 1 mA and the IOL for

each port is 1 mA or less.

Port

Ratings

typ

–0.35

–10

Unit

max

5.0

1.0

µA

1.0

mA

µA

1.5

V

0.5

Hysteresis voltage

High-level threshold

voltage

Low-level threshold

voltage

Current drain *6

Two-pin RC oscillator

Ceramic oscillator

External clock

Standby mode

VHIS

VtH

VtL

RES, INT, SCK, SI, and

OSC1 with Schmitt

specifications*5

• Operating, with the output

n-channel transistors off

IDDOP (1) • With the ports at VDD

VDD

• Figure 2, fosc = 800 kHz (typical)

IDDOP (2) • Figure 3, 4 MHz, divide-by-three circuit used VDD

IDDOP (3) • Figure 3, 4 MHz, divide-by-four circuit used VDD

IDDOP (4) • Figure 3, 400 kHz

VDD

IDDOP (5) • Figure 3, 800 kHz

VDD

• 200 kHz to 1444 kHz, no divider

circuit

• 600 kHz to 4330 kHz, divide-by-

IDDOP (6) three circuit used

VDD

• 800 kHz to 4330 kHz, divide-by-

four circuit used

Output n-channel transistors off, VDD

IDDst VDD = 6 V

Ports at VDD, VDD = 3 V

VDD

0.1 VDD

0.4 VDD

0.8 VDD

0.2 VDD

0.6 VDD

1.5

4

1.5

5

1.5

4

1.0

2.5 mA

1.5

4

1.5

5

0.05

0.025

10

µA

5

Continued on next page.

No. 6278-14/39

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