LC6512A(2001) Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC6512A
(Rev.:2001)

Single-Chip 4-Bit Microcomputer for Control-Oriented Applications (Low-Threshold Input, On-Chip FLT Driver)

SANYO -> Panasonic 

LC6512A, LC6513A

4-7-4. Notes for circuit design

¡ How to fix C3, R6, C2, R2

Fix closed loop (A) discharge time constants C3, R6 and HOLD pin charge time constants C2, R2 so that closed

loop (A) fully discharges before the HOLD input voltage gets lower than VIL at the time of instantaneous break and

the RES input voltage is sure to get lower than VIL (a reset occurs) when V+ rises after instantaneous break where

the HOLD input voltage gets lower than VIL.

™ How to fix C3, R7

Fix RES pin charge time constants C3, R7 so that when power is applied initially or the HOLD mode is released the

ceramic resonator OSC oscillates normally and the RES input voltage exceeds VIH and the program starts running.

£ How to fix R4, R5

Fix Tr bias constants R4, R5 so that when V+ rises after instantaneous break the RES input voltage gets lower than

VIL (brought to L-Level) before the HOLD input voltage exceeds VIH (brought to H- Level).

¢ How to fix C2, R3

Fix HOLD pin charge time constants C2, R3 so that when the HOLD mode is released from the backup mode the

HOLD input voltage does not exceed VOH (not brought to H-Level) until the RES input voltage gets lower than VIL

(brought to L-Level).

Fix C3, R7 and C2, R3 so that the time interval from the moment the HOLD input voltage exceeds VIH until the

moment the RES input voltage exceeds VIH is longer than the ceremic resonator OSC stabilizing time.

∞ When the load is heavy or the polling interval is long

Since Cl discharges largely, increase the capacity of C1 or separate (B) detection from V+ and use a power supply

or signal that rises faster than V+.

4-7-5. Notes for software design

When the HOLD request signal is detected, the HALT instruction is executed immediately. A concrete example is

shown below.

(1) An interrupt is inhibited before polling the HOLD request pin (HOLD pin).

(2) Polling of the HOLD pin and the HALT instruction are programmed consecutively.

[ Concrete example ]

RCTL

BP0

HALT

3

;EXTEN, TMEN ← 0 (External, timer interrupt inhibit)

AAA ;Polling of the HOLD pin (If H-Level, a branch occurs to AAA.)

;The HOLD mode is entered.

AAA:

No.2367–18/24

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