LC6512A(2001) Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC6512A
(Rev.:2001)

Single-Chip 4-Bit Microcomputer for Control-Oriented Applications (Low-Threshold Input, On-Chip FLT Driver)

SANYO -> Panasonic 

LC6512A, LC6513A

4-3. HOLD power-down mode setting

The HOLD mode permits the supply voltage to be lowered and also the power dissipation to be reduced after mode

setting. The HOLD mode can be used in the capacitor or battery-used backup operation during power failure.

Fig. 4-1 HOLD mode and power-down

¡ A failure of the main power supply is detected and a standby request is made. This is hardware-controlled by the

external circuit.

™ The HOLD pin is software-polled or the same signal is applied to the INT pin to test the standby request by

interrupt. Then, the HALT instruction is executed and the HOLD mode is entered. (Note)

£ After the HOLD mode is entered, power-down can be attained by lowering VDD.

¢ After VDD returns to the prescribed voltage, the HOLD pin is set to H-Level and the normal operation returns.

(Note) The HOLD pin input signal is transferred to pseudo input port PO 0 (DPL = 0EH, 20 bit). Therefore, when

polling the HOLD pin, the BP0 or BNP0 instruction is used at DPL = 0EH. (The IP instruction cannot be

used.)

When the BP0 instruction is used for testing, a branch occurs when the input voltage is at high level in the

same manner as for normal input ports.

4-4. HALT mode release

Release by reset

When L-Level is applied to the RES pin, the HALT mode is released and the system reset state is entered.

When the RES pin is set to H-Level again, the normal operation starts. Since the ceremic resonator mode is used for

system clock generation, the release by reset must be performed.

–Notes–

• Since the ceramic resonator mode is used for system clock generation, L-Level must be applied to the RES pin for 5

to 10 ms (oscillation stabilizing time).

Mode change from HALT mode to HOLD Mode

The HALT mode is entered with the execution of the HALT instruction when the HOLD pin is at H-Level.

The HALT mode is changed to the HOLD mode automatically by setting the HOLD pin to L-Level.

Fig. 4-2 Mode change from HALT modeto HOLD mode

No.2367–15/24

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